Issued Patents All Time
Showing 351–375 of 694 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10629510 | Package with embedded heat dissipation features | Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu | 2020-04-21 |
| 10622336 | Manufacturing method of semiconductor package | Feng-Cheng Hsu, Jui-Pin Hung | 2020-04-14 |
| 10566237 | Profile of through via protrusion in 3DIC interconnect | Jiung Wu, Kuan-Liang Lai, Ming-Tsu Chung, Hong-Ye Shih, Ku-Feng Yang +3 more | 2020-02-18 |
| 10546830 | Chip package structure | Shuo-Mao Chen, Feng-Cheng Hsu | 2020-01-28 |
| 10535597 | Semiconductor structure and manufacturing method thereof | Shuo-Mao Chen, Feng-Cheng Hsu | 2020-01-14 |
| 10535632 | Semiconductor package structure and method of manufacturing the same | Feng-Cheng Hsu, Shuo-Mao Chen | 2020-01-14 |
| 10529679 | 3D packages and methods for forming the same | Shang-Yun Hou, Sao-Ling Chiu, Ping-Kang Huang, Wen-Hsin Wei, Wen-Chih Chiou +1 more | 2020-01-07 |
| 10529671 | Package structure and method for forming the same | Hsiao-Wen Lee, Hsien-Wen Liu | 2020-01-07 |
| 10522473 | Alignment mark design for packages | Li-Hsien Huang, Hsien-Wei Chen, Ching-Wen Hsiao, Der-Chyang Yeh, Chen-Hua Yu | 2019-12-31 |
| 10522491 | Semiconductor device and bump formation process | Yi-Li Hsiao, Chen-Hua Yu, Chih-Hang Tung, Cheng-Chang Wei | 2019-12-31 |
| 10515829 | Package system for integrated circuits | Wei-Cheng Wu, Shang-Yun Hou, Chen-Hua Yu | 2019-12-24 |
| 10515930 | Three-layer package-on-package structure and method forming same | Jui-Pin Hung, Feng-Cheng Hsu | 2019-12-24 |
| 10515827 | Method for forming chip package with recessed interposer substrate | Po-Hao Tsai, Po-Yao Chuang, Feng-Cheng Hsu, Shuo-Mao Chen, Techi Wong | 2019-12-24 |
| 10510670 | Pad structure design in fan-out package | Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen | 2019-12-17 |
| 10510690 | Wafer level package (WLP) and method for forming the same | Hsien-Wen Liu | 2019-12-17 |
| 10510561 | Semiconductor device package including conformal metal cap contacting each semiconductor die | Chen-Yu Tsai, Tsung-Shang Wei, Yu-Sheng Lin, Wen-Chih Chiou | 2019-12-17 |
| 10504880 | Method of forming semicondcutor device package | Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shu-Shen Yeh +1 more | 2019-12-10 |
| 10504752 | Integrated passive device package and methods of forming same | Feng-Cheng Hsu, Shuo-Mao Chen, Jui-Pin Hung | 2019-12-10 |
| 10497616 | Embedded 3D interposer structure | Ying-Ching Shih, Jing-Cheng Lin, Wen-Chih Chiou, Chen-Hua Yu | 2019-12-03 |
| 10475769 | Semiconductor package and manufacturing method of the same | Feng-Cheng Hsu, Jui-Pin Hung | 2019-11-12 |
| 10475759 | Integrated circuit structure having dies with connectors of different sizes | Chen-Hua Yu, Jing-Cheng Lin | 2019-11-12 |
| 10468339 | Heterogeneous fan-out structure and method of manufacture | Po-Hao Tsai, Po-Yao Chuang, Techi Wong | 2019-11-05 |
| RE47709 | Forming grounded through-silicon vias in a semiconductor substrate | Chi-Chun Hsieh, Wei-Cheng Wu, Hsiao-Tsung Yen, Hsien-Pin Hu, Shang-Yun Hou | 2019-11-05 |
| 10461009 | 3DIC packaging with hot spot thermal management features | Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu | 2019-10-29 |
| 10446520 | 3D semiconductor package interposer with die cavity | Shang-Yun Hou, Kim Hong Chen, Wensen Hung, Szu-Po Huang | 2019-10-15 |