Issued Patents All Time
Showing 301–325 of 694 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11062997 | Method for forming chip package structure | Techi Wong, Po-Yao Lin, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Chuang | 2021-07-13 |
| 11056464 | Packages with metal line crack prevention design | Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen | 2021-07-06 |
| 11056445 | Package structure with buffer layer sandwiched between encapsulation layer and semiconductor substrate | Hsiao-Wen Lee, Hsien-Wen Liu | 2021-07-06 |
| 11037852 | 3DIC packaging with hot spot thermal management features | Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu | 2021-06-15 |
| 11018081 | Heterogeneous fan-out structure and method of manufacture | Po-Hao Tsai, Po-Yao Chuang, Techi Wong | 2021-05-25 |
| 11011447 | Semiconductor package and method for forming the same | Chin-Hua Wang, Po-Yao Lin, Feng-Cheng Hsu, Wen-Yi Lin, Shu-Shen Yeh | 2021-05-18 |
| 11004771 | Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices | Cheng-Chieh Hsieh, Chi-Hsi Wu, Tsung-Yu Chen, Wensen Hung | 2021-05-11 |
| 11004741 | Profile of through via protrusion in 3DIC interconnect | Jiung Wu, Kuan-Liang Lai, Ming-Tsu Chung, Hong-Ye Shih, Ku-Feng Yang +3 more | 2021-05-11 |
| 10985100 | Chip package with recessed interposer substrate | Po-Hao Tsai, Po-Yao Chuang, Feng-Cheng Hsu, Shuo-Mao Chen, Techi Wong | 2021-04-20 |
| 10971483 | Semiconductor structure and manufacturing method thereof | Jui-Pin Hung, Feng-Cheng Hsu | 2021-04-06 |
| 10971461 | Semiconductor device and method of manufacture | Po-Hao Tsai, Po-Yao Chuang, Ming-Chih Yew | 2021-04-06 |
| 10910267 | Alignment marks in substrate having through-substrate via (TSV) | Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou | 2021-02-02 |
| 10879162 | Integrated fan-out packages | Dai-Jang Chen, Hsiang-Tai Lu, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung +1 more | 2020-12-29 |
| 10872865 | Electric magnetic shielding structure in packages | Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen | 2020-12-22 |
| 10867924 | Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing | Shuo-Mao Chen, Hsien-Wen Liu, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin | 2020-12-15 |
| 10867925 | Method for forming chip package structure | Shuo-Mao Chen, Feng-Cheng Hsu, Po-Yao Lin | 2020-12-15 |
| 10861835 | Solution for reducing poor contact in InFO package | Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih-Ting Lin | 2020-12-08 |
| 10861801 | Wafer level package (WLP) and method for forming the same | Hsien-Wen Liu | 2020-12-08 |
| 10854579 | Semiconductor package structure | Feng-Cheng Hsu | 2020-12-01 |
| 10854567 | 3D packages and methods for forming the same | Shang-Yun Hou, Sao-Ling Chiu, Ping-Kang Huang, Wen-Hsin Wei, Wen-Chih Chiou +1 more | 2020-12-01 |
| 10854563 | Device, semiconductor package and method of manufacturing semiconductor package | Chia-Kuei Hsu, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Lin | 2020-12-01 |
| 10847414 | Embedded 3D interposer structure | Ying-Ching Shih, Jing-Cheng Lin, Wen-Chih Chiou, Chen-Hua Yu | 2020-11-24 |
| 10811389 | Semiconductor package for thermal dissipation | Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu | 2020-10-20 |
| 10804254 | Fan-out package with cavity substrate | Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Meng-Wei Chou, Meng-Liang Lin | 2020-10-13 |
| 10804244 | Semiconductor package structure and method of manufacturing the same | Feng-Cheng Hsu, Shuo-Mao Chen | 2020-10-13 |