Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12362315 | Heterogeneous dielectric bonding scheme | Chen-Hua Yu, Wen-Chih Chiou, Ku-Feng Yang | 2025-07-15 |
| 12322680 | Semiconductor device having backside interconnect structure on through substrate via | Yung-Chi Lin, Hsin-Yu Chen, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen +3 more | 2025-06-03 |
| 12087732 | Isolation bonding film for semiconductor packages and methods of forming the same | Ku-Feng Yang, Yung-Chi Lin, Wen-Chih Chiou, Chen-Hua Yu | 2024-09-10 |
| 12074064 | TSV structure and method forming same | Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou, Chen-Hua Yu | 2024-08-27 |
| 11869869 | Heterogeneous dielectric bonding scheme | Chen-Hua Yu, Wen-Chih Chiou, Ku-Feng Yang | 2024-01-09 |
| 11823979 | Method of forming semiconductor device having backside interconnect structure on through substrate via | Yung-Chi Lin, Hsin-Yu Chen, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen +3 more | 2023-11-21 |
| 11721666 | Isolation bonding film for semiconductor packages and methods of forming the same | Ku-Feng Yang, Yung-Chi Lin, Wen-Chih Chiou, Chen-Hua Yu | 2023-08-08 |
| 11527439 | TSV structure and method forming same | Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou, Chen-Hua Yu | 2022-12-13 |
| 11101240 | Isolation bonding film for semiconductor packages and methods of forming the same | Ku-Feng Yang, Yung-Chi Lin, Wen-Chih Chiou, Chen-Hua Yu | 2021-08-24 |
| 11056419 | Semiconductor device having backside interconnect structure on through substrate via and method of forming the same | Yung-Chi Lin, Hsin-Yu Chen, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen +3 more | 2021-07-06 |
| 11004741 | Profile of through via protrusion in 3DIC interconnect | Jiung Wu, Kuan-Liang Lai, Hong-Ye Shih, Ku-Feng Yang, Tsang-Jiuh Wu +3 more | 2021-05-11 |
| 10566237 | Profile of through via protrusion in 3DIC interconnect | Jiung Wu, Kuan-Liang Lai, Hong-Ye Shih, Ku-Feng Yang, Tsang-Jiuh Wu +3 more | 2020-02-18 |
| 10510641 | Semiconductor device having backside interconnect structure on through substrate via and method of forming the same | Yung-Chi Lin, Hsin-Yu Chen, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen +3 more | 2019-12-17 |
| 10163705 | Profile of through via protrusion in 3DIC interconnect | Jiung Wu, Kuan-Liang Lai, Hong-Ye Shih, Ku-Feng Yang, Tsang-Jiuh Wu +3 more | 2018-12-25 |
| 10074595 | Self-alignment for redistribution layer | Ku-Feng Yang, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen +2 more | 2018-09-11 |
| 9786580 | Self-alignment for redistribution layer | Ku-Feng Yang, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen +2 more | 2017-10-10 |
| 9773701 | Methods of making integrated circuits including conductive structures through substrates | Yuan-Hung Liu, Ku-Feng Yang, Pei-Ching Kuo, Hsin-Yu Chen, Tsang-Jiuh Wu +1 more | 2017-09-26 |
| 9449898 | Semiconductor device having backside interconnect structure through substrate via and method of forming the same | Yung-Chi Lin, Hsin-Yu Chen, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen +3 more | 2016-09-20 |
| 9059262 | Integrated circuits including conductive structures through a substrate and methods of making the same | Yuan-Hung Liu, Ku-Feng Yang, Pei-Ching Kuo, Hsin-Yu Chen, Tsang-Jiuh Wu +1 more | 2015-06-16 |