Issued Patents All Time
Showing 1,601–1,625 of 1,955 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8486823 | Methods of forming through via | Wen-Chih Chiou, Weng-Jin Wu, Jung-Chih Hu | 2013-07-16 |
| 8487410 | Through-silicon vias for semicondcutor substrate and method of manufacture | Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang +4 more | 2013-07-16 |
| 8476116 | Reduction of etch microloading for through silicon vias | Hung-Pin Chang | 2013-07-02 |
| 8476770 | Apparatus and methods for forming through vias | Tung-Liang Shao, Chih-Hang Tung, Hao-Yi Tsai, Mirng-Ji Lii, Da-Yuan Shih | 2013-07-02 |
| 8466059 | Multi-layer interconnect structure for stacked dies | Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue | 2013-06-18 |
| 8455995 | TSVs with different sizes in interposers for bonding dies | Po-Hao Tsai, Jing-Cheng Lin | 2013-06-04 |
| 8450200 | Method for stacked contact with low aspect ratio | Chen-Nan Yeh, Chih-Hsiang Yao, Wen-Kai Wan, Jye-Yen Cheng | 2013-05-28 |
| 8446007 | Non-uniform alignment of wafer bumps with substrate solders | Hung-Jui Kuo, Chung-Shi Liu | 2013-05-21 |
| 8446012 | Interconnect structures | Hai-Ching Chen, Tien-I Bao | 2013-05-21 |
| 8440562 | Germanium-containing dielectric barrier for low-K process | Chung-Shi Liu | 2013-05-14 |
| 8440564 | Schemes for forming barrier layers for copper in interconnect structures | Hai-Ching Chen, Tien-I Bao | 2013-05-14 |
| 8435820 | Patterned substrate for hetero-epitaxial growth of group-III nitride film | Ding-Yuan Chen | 2013-05-07 |
| 8432040 | Interconnection structure design for low RC delay and leakage | Ming-Shih Yeh | 2013-04-30 |
| 8433434 | Near non-adaptive virtual metrology and chamber control | Amy Wang, Jean Wang, Henry Lo, Francis Ko, Chih-Wei Lai +1 more | 2013-04-30 |
| 8426961 | Embedded 3D interposer structure | Ying-Ching Shih, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng | 2013-04-23 |
| 8415691 | Omnidirectional reflector | Ding-Yuan Chen, Wen-Chih Chiou | 2013-04-09 |
| 8411459 | Interposer-on-glass package structures | Jing-Cheng Lin | 2013-04-02 |
| 8405225 | Three-dimensional integrated circuits with protection layers | Wen-Chih Chiou, Weng-Jin Wu, Hung-Jung Tu, Ku-Feng Yang | 2013-03-26 |
| 8399273 | Light-emitting diode with current-spreading region | Ding-Yuan Chen, Wen-Chih Chiou | 2013-03-19 |
| 8395221 | Depletion-free MOS using atomic-layer doping | Jing-Cheng Lin | 2013-03-12 |
| 8387674 | Chip on wafer bonder | Jui-Pin Hung, Weng-Jin Wu, Jean Wang, Wen-Chih Chiou | 2013-03-05 |
| 8377796 | III-V compound semiconductor epitaxy from a non-III-V substrate | Chia-Lin Yu, Ding-Yuan Chen, Wen-Chih Chiou | 2013-02-19 |
| 8377816 | Method of forming electrical connections | Chung-Shi Liu, Shin-Puu Jeng, Mirng-Ji Lii | 2013-02-19 |
| 8373269 | Jigs with controlled spacing for bonding dies onto package substrates | Yi-Li Hsiao, Chung-Shi Liu, Chien Ling Hwang | 2013-02-12 |
| 8368180 | Scribe line metal structure | Shin-Puu Jeng, Hao-Yi Tsai, Shang-Yun Hou, Hsien-Wei Chen, Ming-Yen Chiu | 2013-02-05 |