Issued Patents All Time
Showing 351–375 of 743 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10153249 | Dual-sided integrated fan-out package | Kuo Lung Pan, Wei Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai | 2018-12-11 |
| 10153180 | Semiconductor bonding structures and methods | Meng-Tse Chen, Hsiu-Jen Lin, Wei-Hung Lin, Kuei-Wei Huang, Ming-Da Cheng | 2018-12-11 |
| 10147693 | Methods for stud bump formation | Chien Ling Hwang, Yeong-Jyh Lin, Yi-Li Hsiao, Ming-Da Cheng, Tsai-Tsung Tsai +2 more | 2018-12-04 |
| 10141281 | Substrate and package structure | Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen | 2018-11-27 |
| 10134717 | Semiconductor package, semiconductor device and method of forming the same | Chen-Hua Yu, Chih-Fan Huang, Tsai-Tsung Tsai, Wei-Hung Lin, Ming-Da Cheng | 2018-11-20 |
| 10134700 | Via structure for packaging and a method of forming | Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo | 2018-11-20 |
| 10134703 | Package on-package process for applying molding compound | Meng-Tse Chen, Wei-Hung Lin, Sheng-Yu Wu, Bor-Ping Jang, Ming-Da Cheng +6 more | 2018-11-20 |
| 10134699 | Packages with solder ball revealed through layer | Yu-Hsiang Hu, Wei-Yu Chen, Ming-Da Cheng, Hung-Jui Kuo | 2018-11-20 |
| 10125014 | Integrated circuit package and method of forming same | Kuo Lung Pan, Hao-Yi Tsai, Yu-Feng Chen, Yu-Jen Cheng | 2018-11-13 |
| 10128206 | Conductive pillar structure | Chih-Wei Lin, Ming-Da Cheng, Wen-Hsiung Lu, Meng-Wei Chou, Hung-Jui Kuo | 2018-11-13 |
| 10115690 | Method of manufacturing micro pins and isolated conductive micro pin | Ying-Jui Huang, Hsin-Hung Liao, Chien Ling Hwang | 2018-10-30 |
| 10109612 | Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices | Kuei-Wei Huang, Hsiu-Jen Lin, Ai-Tee Ang, Ming-Da Cheng | 2018-10-23 |
| 10109618 | Bonding structure between semiconductor device package | James Hu, Ming-Da Cheng | 2018-10-23 |
| 10090254 | Wafer alignment methods in die sawing process | Yu-Hsiang Hu, Ming-Da Cheng | 2018-10-02 |
| 10062654 | Semicondcutor structure and semiconductor manufacturing process thereof | Yu-Chia Lai, Chen-Hua Yu, Chang-Pin Huang, Hsien-Ming Tu, Hung-Yi Kuo +3 more | 2018-08-28 |
| 10062659 | System and method for an improved fine pitch joint | Cheng-Ting Chen, Wen-Hsiung Lu, Ming-Da Cheng, Mirng-Ji Lii | 2018-08-28 |
| 10049986 | Package structures and methods of making the same | Zi-Jheng Liu, Hung-Jui Kuo, Yu-Hsiang Hu | 2018-08-14 |
| 10049894 | Package structures and methods for forming the same | Hsien-Liang Meng, Wei-Hung Lin, Yu-Min Liang, Ming-Che Ho, Hung-Jui Kuo +1 more | 2018-08-14 |
| 10049889 | Method of fabricating package structures | Yu-Hsiang Hu, Hung-Jui Kou, Sih-Hao Liao | 2018-08-14 |
| 10050000 | Bump-on-trace structures with high assembly yield | Chih-Fan Huang, Chen-Shien Chen, Ming-Da Cheng, Tin-Hao Kuo, Yi-Teh Chou | 2018-08-14 |
| 10043778 | Methods of packaging semiconductor devices and packaged semiconductor devices | Chen-Hua Yu, Meng-Tse Chen, Hui-Min Huang, Chih-Fan Huang, Ming-Da Cheng | 2018-08-07 |
| 10032734 | Semiconductor package system and method | Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chen-Hua Yu | 2018-07-24 |
| 10020211 | Wafer-level molding chase design | Chen-Hua Yu, Hui-Min Huang, Chih-Fan Huang, Ming-Da Cheng, Meng-Tse Chen +2 more | 2018-07-10 |
| 10015888 | Interconnect joint protective layer apparatus and method | Cheng-Ting Chen, Hsuan-Ting Kuo, Hsien-Wei Chen, Wen-Hsiung Lu, Ming-Da Cheng | 2018-07-03 |
| 10014260 | Package structure and method for forming the same | Yi-Da Tsai, Cheng Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng +1 more | 2018-07-03 |