Issued Patents All Time
Showing 1,226–1,250 of 1,955 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9728457 | System, structure, and method of manufacturing a semiconductor substrate stack | Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou | 2017-08-08 |
| 9728508 | Semiconductor device and method of manufacture | Jing-Cheng Lin, Po-Hao Tsai | 2017-08-08 |
| 9728427 | Method for manufacturing semiconductor structure | Chih-Fan Huang, Chun-Hung Lin, Ming-Da Cheng, Chung-Shi Liu, Mirng-Ji Lii | 2017-08-08 |
| 9722025 | FinFETs having dielectric punch-through stoppers | Cheng-Hung Chang, Chen-Nan Yeh | 2017-08-01 |
| 9711470 | Package on package structure and method for forming the same | Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin | 2017-07-18 |
| 9711379 | 3D stacked-chip package | Wen-Ching Tsai, Ming-Fa Chen | 2017-07-18 |
| 9711458 | Structure and formation method for chip package | Wen-Chih Chiou | 2017-07-18 |
| 9711373 | Method of fabricating a gate dielectric for high-k metal gate devices | Che-Hao Chang, Cheng-Hao Hou, Tai-Bor Wu | 2017-07-18 |
| 9704826 | Chip on package structure and method | Der-Chyang Yeh, Kuo-Chung Yee, Jui-Pin Hung | 2017-07-11 |
| 9698081 | 3D chip-on-wafer-on-substrate structure with via last process | Ming-Fa Chen, Wen-Ching Tsai | 2017-07-04 |
| 9698325 | Light-emitting device including reflective layer | Ding-Yuan Chen, Chia-Lin Yu, Wen-Chih Chiou | 2017-07-04 |
| 9698071 | Die packages and methods of manufacture thereof | Chuei-Tang Wang | 2017-07-04 |
| 9691706 | Multi-chip fan out package and methods of forming the same | Jing-Cheng Lin, Jui-Pin Hung | 2017-06-27 |
| 9685426 | Package-on-package semiconductor device | Der-Chyang Yeh | 2017-06-20 |
| 9679882 | Method of multi-chip wafer level packaging | Chih-Hang Tung, Chun-Hui Yu, Da-Yuan Shih | 2017-06-13 |
| 9679783 | Molding wafer chamber | Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung, Szu-Wei Lu, Shin-Puu Jeng | 2017-06-13 |
| 9673082 | Method of fabricating semiconductor device isolation structure | Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen | 2017-06-06 |
| 9666520 | 3D stacked-chip package | Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai | 2017-05-30 |
| 9666522 | Alignment mark design for packages | Li-Hsien Huang, Hsien-Wei Chen, Ching-Wen Hsiao, Der-Chyang Yeh, Shin-Puu Jeng | 2017-05-30 |
| 9666487 | Method for manufacturing germanium-based CMOS comprising forming silicon cap over PMOS region having a thickness less than that over NMOS region | Jing-Cheng Lin | 2017-05-30 |
| 9659896 | Interconnect structures for wafer level package and methods of forming same | Chih-Hao Chang, Tsung-Hsien Chiang, Guan-Yu Chen, Wei Sen Chang, Tin-Hao Kuo +1 more | 2017-05-23 |
| 9661794 | Method of manufacturing package structure | Shou-Zen Chang, Chung-Shi Liu, Kai-Chiang Wu, Wei-Ting Lin | 2017-05-23 |
| 9659918 | POP structures with dams encircling air gaps and methods for forming the same | Dean Wang, Chen-Shien Chen, Chung-Shi Liu, Jiun Yi Wu | 2017-05-23 |
| 9659863 | Semiconductor devices, multi-die packages, and methods of manufacture thereof | Hsien-Wei Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Shih-Peng Tai | 2017-05-23 |
| 9653442 | Integrated circuit package and methods of forming same | Kuo-Chung Yee, Mirng-Ji Lii, Chien-Hsun Lee, Jiun Yi Wu | 2017-05-16 |