Issued Patents All Time
Showing 1,201–1,225 of 1,955 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9799625 | Semiconductor structure and manufacturing method thereof | Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang +9 more | 2017-10-24 |
| 9793140 | Staggered via redistribution layer (RDL) for a package and a method for forming the same | Chung-Shi Liu, Hung-Jui Kuo | 2017-10-17 |
| 9793230 | Semiconductor structure and method of forming | Yu-Hsiang Hu, Hung-Jui Kuo | 2017-10-17 |
| 9793192 | Formation of through via before contact processing | Wen-Chih Chiou, Weng-Jin Wu | 2017-10-17 |
| 9786618 | Semiconductor structure and manufacturing method thereof | Chang-Pin Huang, Hsien-Ming Tu, Ching-Jung Yang, Shih-Wei Liang, Hung-Yi Kuo +3 more | 2017-10-10 |
| 9786631 | Device package with reduced thickness and method for forming same | Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu | 2017-10-10 |
| 9786599 | Package structures and method of forming the same | An-Jhih Su | 2017-10-10 |
| 9773768 | Method and structure of three-dimensional chip stacking | Wen-Chih Chiou, Yung-Chi Lin | 2017-09-26 |
| 9773730 | Semiconductor arrangement and formation thereof | Chung-Hao Tsai, Jeng-Shien Hsieh, Chuei-Tang Wang | 2017-09-26 |
| 9773757 | Devices, packaged semiconductor devices, and semiconductor device packaging methods | Kuo-Chung Yee | 2017-09-26 |
| 9767957 | Method of manufacturing a tunable three dimensional inductor | Monsen Liu, Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang | 2017-09-19 |
| 9768145 | Methods of forming multi-die package structures including redistribution layers | Kuo-Chung Yee, Tsung-Ding Wang, Chien-Hsun Lee | 2017-09-19 |
| 9768105 | Rigid interconnect structures in package-on-package assemblies | Mirng-Ji Lii, Chien-Hsiun Lee, Yung Ching Chen, Jiun Yi Wu | 2017-09-19 |
| 9761566 | Multi-die structure and method of forming same | Po-Hao Tsai, Jing-Cheng Lin, Li-Hui Cheng | 2017-09-12 |
| 9761522 | Wireless charging package with chip integrated in coil center | Chiang-Jui Chu, Chung-Shi Liu, Hao-Yi Tsai, Ming Hung Tseng, Hung-Yi Kuo | 2017-09-12 |
| 9754918 | 3D chip-on-wafer-on-substrate structure with via last process | Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh | 2017-09-05 |
| 9754805 | Packaging method and structure | Ching-Hua Hsieh, Chung-Shi Liu, Ming-Da Cheng | 2017-09-05 |
| 9748189 | Multi-chip package structure and method of forming same | Jui-Pin Hung, Jing-Cheng Lin, Der-Chyang Yeh | 2017-08-29 |
| 9741694 | Semiconductor structure and method of manufacturing the same | Ming-Fa Chen, Sung-Feng Yeh | 2017-08-22 |
| 9741689 | 3-D package having plurality of substrates | Chin-Chuan Chang, Jing-Cheng Lin | 2017-08-22 |
| 9741690 | Redistribution layers in semiconductor packages and methods of forming same | Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh +1 more | 2017-08-22 |
| 9735129 | Semiconductor packages and methods of forming the same | Hsien-Wei Chen, Jie Chen, Der-Chyang Yeh, Shin-Puu Jeng | 2017-08-15 |
| 9735118 | Antennas and waveguides in InFO structures | Chuei-Tang Wang, Chung-Hao Tsai, Jeng-Shien Hsieh, Wei-Heng Lin | 2017-08-15 |
| 9735042 | Dielectric punch-through stoppers for forming FinFETs having dual Fin heights | Shih-Ting Hung, Cheng-Hung Chang, Chen-Yi Lee, Chen-Nan Yeh | 2017-08-15 |
| 9735131 | Multi-stack package-on-package structures | An-Jhih Su | 2017-08-15 |