Issued Patents All Time
Showing 26–50 of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11489111 | Reversible resistive memory logic gate device | Hsueh-Chung Chen, Junli Wang | 2022-11-01 |
| 11316029 | Sacrificial fin for contact self-alignment | Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz, Eric R. Miller | 2022-04-26 |
| 11227801 | Formation of contacts for semiconductor devices | Ruilong Xie, Heng Wu, Julien Frougier | 2022-01-18 |
| 11222981 | Three-dimensional field effect device | Huimei Zhou, Shogo Mochizuki, Peng Xu, Nicolas Loubet | 2022-01-11 |
| 11205590 | Self-aligned contacts for MOL | Adra Carr, Ruilong Xie, Kangguo Cheng | 2021-12-21 |
| 11205587 | Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability | Hemanth Jagannathan, Raghuveer R. Patlolla, Cornelius Brown Peethala | 2021-12-21 |
| 11183593 | Three-dimensional field effect device | Huimei Zhou, Shogo Mochizuki, Peng Xu, Nicolas Loubet | 2021-11-23 |
| 11171051 | Contacts and liners having multi-segmented protective caps | Jennifer Fullam, Christopher J. Waskiewicz, Muthumanickam Sankarapandian | 2021-11-09 |
| 11164778 | Barrier-free vertical interconnect structure | Junli Wang, Hsueh-Chung Chen, Yann Mignot, Lawrence A. Clevenger | 2021-11-02 |
| 11158543 | Silicide formation for source/drain contact in a vertical transport field-effect transistor | Heng Wu, Ruilong Xie, Huai Huang | 2021-10-26 |
| 11114382 | Middle-of-line interconnect having low metal-to-metal interface resistance | Alex Varghese, Richard A. Conti | 2021-09-07 |
| 11081566 | Self-aligned contacts for vertical field effect transistors | Ekmini Anuja De Silva, Sivananda K. Kanakasabapathy | 2021-08-03 |
| 11063126 | Metal contact isolation for semiconductor structures | Yann Mignot, Hsueh-Chung Chen, James J. Kelly | 2021-07-13 |
| 11011417 | Method and structure of metal cut | Ruilong Xie, Andrew M. Greene, Veeraraghavan S. Basker | 2021-05-18 |
| 10971490 | Three-dimensional field effect device | Huimei Zhou, Shogo Mochizuki, Peng Xu, Nicolas Loubet | 2021-04-06 |
| 10971356 | Stack viabar structures | Hsueh-Chung Chen, Yann Mignot, James J. Kelly, Terence B. Hook | 2021-04-06 |
| 10957552 | Extreme ultraviolet lithography patterning with directional deposition | Yongan Xu, Ekmini Anuja De Silva, Yann Mignot | 2021-03-23 |
| 10943990 | Gate contact over active enabled by alternative spacer scheme and claw-shaped cap | Andrew M. Greene, Victor Chan, Gangadhara Raja Muthinti, Veeraraghavan S. Basker, Junli Wang +1 more | 2021-03-09 |
| 10896972 | Self-aligned contact for vertical field effect transistor | Brent A. Anderson, Steven R. Bentley, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie | 2021-01-19 |
| 10879375 | Gate tie-down enablement with inner spacer | Andre P. Labonte, Lars Liebmann, Sanjay C. Mehta | 2020-12-29 |
| 10832961 | Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor | Ruilong Xie, Veeraraghavan S. Basker, Andre P. Labonte, Chanro Park | 2020-11-10 |
| 10832943 | Gate contact over active region with self-aligned source/drain contact | Cheng Chi, Kangguo Cheng, Ruilong Xie | 2020-11-10 |
| 10833173 | Low-resistance top contact on VTFET | Christopher J. Waskiewicz, Hari Prasad Amanapu, Hemanth Jagannathan | 2020-11-10 |
| 10818548 | Method and structure for cost effective enhanced self-aligned contacts | Kafai Lai, Chih-Chao Yang, Yongan Xu | 2020-10-27 |
| 10804148 | Buried contact to provide reduced VFET feature-to-feature tolerance requirements | Jeffrey C. Shearer, Robert C. Wong, Ruilong Xie | 2020-10-13 |