Issued Patents All Time
Showing 201–225 of 549 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10497690 | Semiconductor package, method for forming semiconductor package, and method for forming semiconductor assembly | Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Ying-Ching Shih, Szu-Wei Lu | 2019-12-03 |
| 10497616 | Embedded 3D interposer structure | Ying-Ching Shih, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu | 2019-12-03 |
| 10490474 | Die-on-interposer assembly with dam structure and method of manufacturing the same | Chih-Wei Wu, Szu-Wei Lu | 2019-11-26 |
| 10483234 | Chip packages and methods of manufacture thereof | Chih-Wei Wu, Szu-Wei Lu, Ying-Ching Shih | 2019-11-19 |
| 10475759 | Integrated circuit structure having dies with connectors of different sizes | Shin-Puu Jeng, Chen-Hua Yu | 2019-11-12 |
| 10461069 | Hybrid bonding with through substrate via (TSV) | — | 2019-10-29 |
| 10438934 | Package-on-package structure and manufacturing method thereof | Shih-Ting Lin, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu | 2019-10-08 |
| 10439042 | Semiconductor device and fabrication method thereof | — | 2019-10-08 |
| 10366960 | Fan-out package and methods of forming thereof | Wan-Ting Shih, Nai-Wei Liu, Cheng-Lin Huang | 2019-07-30 |
| 10361161 | Semiconductor device and method of manufacture | Chen-Hua Yu, Po-Hao Tsai | 2019-07-23 |
| 10354982 | Integrated fan-out structure with guiding trenches in buffer layer | Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung | 2019-07-16 |
| 10347612 | Solution for reducing poor contact in InFO package | Chen-Hua Yu, Szu-Wei Lu, Shih-Ting Lin, Shin-Puu Jeng | 2019-07-09 |
| 10340205 | Through substrate vias with improved connections | Ku-Feng Yang | 2019-07-02 |
| 10340253 | Package structure and method of manufacturing the same | Shu-Hang Liao, Chih-Wei Wu, Szu-Wei Lu, Ying-Ching Shih | 2019-07-02 |
| 10340247 | Method for forming hybrid bonding with through substrate via (TSV) | — | 2019-07-02 |
| 10297550 | 3D IC architecture with interposer and interconnect structure for bonding dies | Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jiun-Ren Lai, Yung-Chi Lin | 2019-05-21 |
| 10297494 | Raised via for terminal connections on different planes | Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming-Shih Yeh +1 more | 2019-05-21 |
| 10290609 | Semiconductor device and manufacturing method of the same | Ying-Ching Shih, Pu Wang, Chen-Hua Yu | 2019-05-14 |
| 10290559 | Thermal dissipation through seal rings in 3DIC structure | Shih-Yi Syu | 2019-05-14 |
| 10290513 | Carrier warpage control for three dimensional integrated circuit (3DIC) stacking | Shih-Ting Lin, Chen-Hua Yu | 2019-05-14 |
| 10276516 | Semiconductor package | Chin-Chuan Chang, Jui-Pin Hung | 2019-04-30 |
| 10269778 | Package on package (PoP) bonding structures | Jui-Pin Hung, Po-Hao Tsai | 2019-04-23 |
| 10269762 | Rework process and tool design for semiconductor package | Shih-Ting Lin, Justin Huang, Tsung-Fu Tsai, Chen-Hua Yu | 2019-04-23 |
| 10269731 | Apparatus for dicing interposer assembly | Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu-Wei Lu | 2019-04-23 |
| 10269685 | Interconnect structure for package-on-package devices | Jui-Pin Hung, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh +1 more | 2019-04-23 |