Issued Patents All Time
Showing 151–175 of 549 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840218 | Semiconductor device and method of manufacture | Chen-Hua Yu, Po-Hao Tsai | 2020-11-17 |
| 10840215 | Sawing underfill in packaging processes | Szu-Wei Lu, Ying-Da Wang, Li-Chung Kuo | 2020-11-17 |
| 10833039 | Multi-chip fan out package and methods of forming the same | Chen-Hua Yu, Jui-Pin Hung | 2020-11-10 |
| 10825693 | Carrier warpage control for three dimensional integrated circuit (3DIC) stacking | Shih-Ting Lin, Chen-Hua Yu | 2020-11-03 |
| 10818607 | Semiconductor device and method of manufacture | Chen-Hua Yu, Po-Hao Tsai | 2020-10-27 |
| 10818583 | Semiconductor devices, methods of manufacture thereof, and semiconductor device packages | I-Ting Chen, Ying-Ching Shih, Po-Hao Tsai, Szu-Wei Lu | 2020-10-27 |
| 10811298 | Patterned carrier wafers and methods of making and using the same | — | 2020-10-20 |
| 10804187 | Fan-out wafer level package structure | — | 2020-10-13 |
| 10804247 | Chip package structure with conductive shielding film | Chen-Hua Yu, An-Jhih Su, Po-Hao Tsai | 2020-10-13 |
| 10784123 | Integrated circuit packages and methods of forming same | Li-Hui Cheng, Po-Hao Tsai | 2020-09-22 |
| 10770365 | Package structures and methods of forming the same | Chen-Hua Yu, Hsien-Pin Hu, Szu-Wei Lu, Shang-Yun Hou, Wen-Hsin Wei +2 more | 2020-09-08 |
| 10763132 | Release film as isolation film in package | Li-Hui Cheng, Po-Hao Tsai | 2020-09-01 |
| 10748869 | Protective layer for contact pads in fan-out interconnect structure and method of forming same | Chin-Chuan Chang, Tsei-Chung Fu | 2020-08-18 |
| 10741520 | Method of controlling bump height variation | Po-Hao Tsai | 2020-08-11 |
| 10741511 | Fan-out package and methods of forming thereof | Wan-Ting Shih, Nai-Wei Liu, Cheng-Lin Huang | 2020-08-11 |
| 10741467 | Die-on-interposer assembly with dam structure and method of manufacturing the same | Chih-Wei Wu, Szu-Wei Lu | 2020-08-11 |
| 10720403 | Integrated fan-out package structures with recesses in molding compound | Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung | 2020-07-21 |
| 10699981 | Non-vertical through-via in package | Cheng-Lin Huang, Jung-Hua Chang, Jy-Jie Gau | 2020-06-30 |
| 10692764 | Alignment marks in substrate having through-substrate via (TSV) | Hsin Chang, Fang Wen Tsai, Wen-Chih Chiou, Shin-Puu Jeng | 2020-06-23 |
| 10672752 | Semiconductor package and manufacturing method thereof | Li-Hui Cheng, Po-Hao Tsai | 2020-06-02 |
| 10672723 | Semiconductor package | Chin-Chuan Chang, Jui-Pin Hung | 2020-06-02 |
| 10658347 | Semiconductor packages and methods of forming the same | Chen-Hua Yu, Po-Hao Tsai | 2020-05-19 |
| 10658195 | Metal oxide layered structure and methods of forming the same | Cheng-Lin Huang | 2020-05-19 |
| 10643836 | Bonded semiconductor structures | — | 2020-05-05 |
| 10636748 | Package structure | Chen-Hua Yu, Tsei-Chung Fu | 2020-04-28 |