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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Patrick Morrow — 189 Patents

Intel: 188 patents #68 of 30,777Top 1%
INIntle: 1 patents #1 of 16Top 7%
Portland, OR: #31 of 9,213 inventorsTop 1%
Oregon: #66 of 28,073 inventorsTop 1%
Overall (All Time): #3,834 of 4,157,543Top 1%
189 Patents All Time
Patrick Morrow has been granted 189 US patents while listed as an inventor at Intel. The first was granted in 2002 and the most recent in December 2025. Patrick Morrow ranks #3,834 of 4,157,543 US inventors in our database (top 0.09%). Patent records list Patrick Morrow in Portland, OR, US.

Patents per Year

Patents granted per year, 2002 to 2025Bar chart with a peak of 31 patents in 2023.peak 312002: 2 patents20022003: 2 patents2004: 1 patents2005: 4 patents20052006: 3 patents2007: 5 patents2008: 6 patents20082010: 5 patents2011: 1 patents2012: 1 patents20122013: 1 patents2014: 1 patents2015: 1 patents20152016: 4 patents2017: 8 patents2018: 4 patents20182019: 15 patents2020: 14 patents2021: 21 patents20212022: 27 patents2023: 31 patents2024: 23 patents20242025: 9 patents2025

Issued Patents All Time

Showing 26–50 of 189 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11942526 Integrated circuit contact structures Glenn A. Glass, Anand S. Murthy, Rishabh Mehandru 2024-03-26 $33,708,000
11935891 Non-silicon N-type and P-type stacked transistors for integrated circuit devices Gilbert Dewey, Ravi Pillarisetty, Rishabh Mehandru, Cheng-Ying Huang, Willy Rachmady +1 more 2024-03-19 $28,784,000
11935933 Backside contact structures and fabrication for metal on both sides of devices Rishabh Mehandru, Aaron D. Lilak, Kimin Jun 2024-03-19 $28,784,000
11916118 Stacked source-drain-gate connection and process for forming such Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Anh Phan, Willy Rachmady +2 more 2024-02-27 $28,450,000
11894372 Stacked trigate transistors with dielectric isolation and process for forming such Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron D. Lilak, Anh Phan +2 more 2024-02-06 $35,892,000
11894262 Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures Aaron D. Lilak, Rishabh Mehandru 2024-02-06 $35,892,000
11869894 Metallization structures for stacked device connectivity and their methods of fabrication Aaron D. Lilak, Anh Phan, Willy Rachmady, Gilbert Dewey, Jessica M. Torres +6 more 2024-01-09 $30,329,000
11854894 Integrated circuit device structures and double-sided electrical testing Valluri Rao, Rishabh Mehandru, Doug B. Ingerly, Kimin Jun, Kevin P. O'Brien +3 more 2023-12-26 $39,948,000
11830933 Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Anh Phan +2 more 2023-11-28 $31,872,000
11798838 Capacitance reduction for semiconductor devices based on wafer bonding Ehren Mannebach, Aaron D. Lilak, Rishabh Mehandru, Hui Jae Yoo, Kevin Lin 2023-10-24 $20,059,000
11776898 Sidewall interconnect metallization structures for integrated circuit devices Aaron D. Lilak, Anh Phan, Gilbert Dewey, Willy Rachmady 2023-10-03 $24,984,000
11769814 Device including air gapping of gate spacers and other dielectrics and process for providing such Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Kevin Lin, Tristan A. Tronic 2023-09-26 $20,953,000
11764104 Forming an oxide volume within a fin Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach +3 more 2023-09-19 $20,015,000
11764263 Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches Ehren Mannebach, Anh Phan, Aaron D. Lilak, Willy Rachmady, Gilbert Dewey +3 more 2023-09-19 $20,015,000
11749649 Composite IC chips including a chiplet embedded within metallization layers of a host IC chip Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Gerald Pasdast, Van H. Le 2023-09-05 $19,899,000
11742346 Interconnect techniques for electrically connecting source/drain regions of stacked transistors Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Ehren Mannebach +4 more 2023-08-29 $19,273,000
11721649 Microelectronic assemblies Adel A. Elsherbini, Henning Braunisch, Kimin Jun, Brennen Mueller, Shawna M. Liff +2 more 2023-08-08 $22,376,000
11699637 Vertically stacked transistor devices with isolation wall structures containing an electrical conductor Aaron D. Lilak, Anh Phan, Stephanie A. Bojarski 2023-07-11 $21,736,000
11694986 Vias in composite IC chip structures Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Mauro Kobrinksy, Van H. Le +1 more 2023-07-04
11676966 Stacked transistors having device strata with different channel widths Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz +4 more 2023-06-13 $22,204,000
11672133 Vertically stacked memory elements with air gap Aaron D. Lilak, Hui Jae Yoo, Sean T. Ma, Scott B. Clendenning, Abhishek A. Sharma +2 more 2023-06-06 $21,341,000
11664377 Forksheet transistor architectures Aaron D. Lilak, Rishabh Mehandru, Ehren Mannebach, Willy Rachmady 2023-05-30 $16,378,000
11664373 Isolation walls for vertically stacked transistor structures Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru 2023-05-30 $16,378,000
11658221 Backside contact structures and fabrication for metal on both sides of devices Rishabh Mehandru, Aaron D. Lilak, Kimin Jun 2023-05-23 $11,397,000
11658183 Metallization structures under a semiconductor device layer Aaron D. Lilak, Rishabh Mehandru, Stephen M. Cea 2023-05-23 $11,397,000