Issued Patents All Time
Showing 451–475 of 584 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7300867 | Dual damascene interconnect structures having different materials for line and via conductors | Edward C. Cooney, III, Anthony K. Stamper, William T. Motsiff, Michael Lane, Andrew H. Simon | 2007-11-27 |
| 7288475 | Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner | Anthony K. Stamper | 2007-10-30 |
| 7285477 | Dual wired integrated circuit chips | Kerry Bernstein, Timothy J. Dalton, Mark D. Jaffe, Paul D. Kartschoke, Anthony K. Stamper | 2007-10-23 |
| 7285474 | Air-gap insulated interconnections | Brent A. Anderson, Andres Bryant, Anthony K. Stamper | 2007-10-23 |
| 7262451 | High performance embedded DRAM technology with strained silicon | Jack A. Mandelman, Geng Wang | 2007-08-28 |
| 7256503 | Chip underfill in flip-chip technologies | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter, David L. Questad | 2007-08-14 |
| 7232695 | Method and apparatus for completely covering a wafer with a passivating material | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter, Jeffrey S. Zimmerman | 2007-06-19 |
| 7232711 | Method and structure to prevent circuit network charging during fabrication of integrated circuits | Kirk D. Peterson | 2007-06-19 |
| 7231617 | Determination of grain sizes of electrically conductive lines in semiconductor integrated circuits | Fen Chen, Jason P. Gill, Baozhen Li, Timothy D. Sullivan | 2007-06-12 |
| 7227230 | Low-K gate spacers by fluorine implantation | Jack A. Mandelman, William R. Tonti | 2007-06-05 |
| 7207096 | Method of manufacturing high performance copper inductors with bond pads | William T. Motsiff, Erick G. Walton | 2007-04-24 |
| 7205627 | Image sensor cells | James W. Adkisson, John J. Ellis-Monaghan, Mark D. Jaffe, Richard J. Rassel | 2007-04-17 |
| 7205591 | Pixel sensor cell having reduced pinning layer barrier potential and method thereof | James W. Adkisson, Andres Bryant, John J. Ellis-Monaghan, Mark D. Jaffe, Jerome B. Lasky +1 more | 2007-04-17 |
| 7193289 | Damascene copper wiring image sensor | James W. Adkisson, Mark D. Jaffe, Robert K. Leidy, Anthony K. Stamper | 2007-03-20 |
| 7193423 | Wafer-to-wafer alignments | Timothy J. Dalton, Mark D. Jaffe, Stephen E. Luce, Edmund J. Sprogis | 2007-03-20 |
| 7180187 | Interlayer connector for preventing delamination of semiconductor device | John A. Fitzsimmons, Anthony K. Stamper | 2007-02-20 |
| 7176119 | Method of fabricating copper damascene and dual damascene interconnect wiring | William R. Hill, Kenneth F. McAvey, Jr., Thomas L. McDevitt, Anthony K. Stamper, Arthur C. Winslow +1 more | 2007-02-13 |
| 7176583 | Damascene patterning of barrier layer metal for C4 solder bumps | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter | 2007-02-13 |
| 7173303 | FIN field effect transistor with self-aligned gate | Jerome B. Lasky, Jed H. Rankin | 2007-02-06 |
| 7169698 | Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner | Anthony K. Stamper | 2007-01-30 |
| 7129545 | Charge modulation network for multiple power domains for silicon-on-insulator technology | David Cain, Norman J. Rohrer, Daryl M. Seitzer, Steven H. Voldman | 2006-10-31 |
| 7112470 | Chip dicing | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter | 2006-09-26 |
| 7087997 | Copper to aluminum interlayer interconnect using stud and via liner | Lloyd Burrell, Edward E. Cooney, III, John E. Heidenreich, III, Hyun Koo Lee, Mark D. Levy +6 more | 2006-08-08 |
| 7073702 | Self-locking wire bond structure and method of making the same | John A. Fitzsimmons, Anthony K. Stamper | 2006-07-11 |
| 7037824 | Copper to aluminum interlayer interconnect using stud and via liner | Lloyd Burrell, Edward E. Cooney, III, John E. Heidenreich, III, Hyun Koo Lee, Mark D. Levy +6 more | 2006-05-02 |