Issued Patents All Time
Showing 501–525 of 584 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6503798 | Low resistance strap for high density trench DRAMS | Ramachandra Divakaruni, Herbert L. Ho, Akira Sudo | 2003-01-07 |
| 6501131 | Transistors having independently adjustable parameters | Rama Divakaruni, Jack A. Mandelman, Rajesh Rengarajan | 2002-12-31 |
| 6495439 | Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby | Son V. Nguyen, Reinhard Stengl | 2002-12-17 |
| 6486505 | Semiconductor contact and method of forming the same | Thomas Rupp, Peter D. Hoh, Senthil Srinivasan | 2002-11-26 |
| 6479368 | Method of manufacturing a semiconductor device having a shallow trench isolating region | Jack A. Mandelman, Mutsuo Morikado, Herbert L. Ho | 2002-11-12 |
| 6448173 | Aluminum-based metallization exhibiting reduced electromigration and method therefor | Lawrence A. Clevenger, Ronald G. Filippi, Kenneth P. Rodbell, Roy Iggulden, Chao-Kun Hu +3 more | 2002-09-10 |
| 6436749 | Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion | William R. Tonti, Claude L. Bertin, Russell J. Houghton, Jack A. Mandelman, Wilbur D. Pricer | 2002-08-20 |
| 6429474 | Storage-capacitor electrode and interconnect | Gary B. Bronner, David E. Kotecki, Carl Radens | 2002-08-06 |
| 6426247 | Low bitline capacitance structure and method of making same | Ramachandra Divakaruni, Jack A. Mandelman, Rajesh Rengarajan | 2002-07-30 |
| 6420749 | Trench field shield in trench isolation | Ramachandra Divakaruni, Edward W. Kiewra, Jack A. Mandelman, Carl Radens, William R. Tonti | 2002-07-16 |
| 6413870 | Process of removing CMP scratches by BPSG reflow and integrated circuit chip formed thereby | William Francis Landers | 2002-07-02 |
| 6403423 | Modified gate processing for optimized definition of array and logic devices on same chip | Mary E. Weybright, Gary B. Bronner, Richard A. Conti, Ramachandra Divakaruni, Peter D. Hoh +1 more | 2002-06-11 |
| 6395594 | Method for simultaneously forming a storage-capacitor electrode and interconnect | David E. Kotecki, Carl Radens, Gary B. Bronner | 2002-05-28 |
| 6380027 | Dual tox trench dram structures and process using V-groove | Toshiharu Furukawa, Edward W. Kiewra, Jack A. Mandelman, Carl Radens, William R. Tonti +1 more | 2002-04-30 |
| 6369423 | Semiconductor device with a thin gate stack having a plurality of insulating layers | Tokuhisa Ohiwa, Katsuya Okumura, Jun-ichi Shiozawa | 2002-04-09 |
| 6350653 | Embedded DRAM on silicon-on-insulator substrate | James W. Adkisson, Ramachandra Divakaruni, Jack A. Mandelman | 2002-02-26 |
| 6344383 | Structure and method for dual gate oxidation for CMOS technology | Wayne S. Berry, Jack A. Mandelman, William R. Tonti | 2002-02-05 |
| 6344389 | Self-aligned damascene interconnect | Gary B. Bronner, Carl Radens | 2002-02-05 |
| 6339001 | Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist | Gary B. Bronner | 2002-01-15 |
| 6326260 | Gate prespacers for high density, high performance DRAMs | Ramachandra Divakaruni, James W. Adkisson, Mary E. Weybright, Scott D. Halle, Heon Lee | 2001-12-04 |
| 6274467 | Dual work function gate conductors with self-aligned insulating cap | Louis L. Hsu, Jack A. Mandelman, Carl Radens, William R. Tonti | 2001-08-14 |
| 6261950 | Self-aligned metal caps for interlevel metal connections | Dirk Tobben | 2001-07-17 |
| 6261914 | Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer | Ramachandra Divakaruni, Carl Radens, Jeremy K. Stephens | 2001-07-17 |
| 6259129 | Strap with intrinsically conductive barrier | Rajarao Jammy, Jack A. Mandelman, Carl Radens | 2001-07-10 |
| 6258689 | Low resistance fill for deep trench capacitor | Gary B. Bronner, Jack A. Mandelman, Rick L. Mohler, Carl Radens, William R. Tonti | 2001-07-10 |