Issued Patents All Time
Showing 526–550 of 584 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6252271 | Flash memory structure using sidewall floating gate and method for forming the same | Louis L. Hsu, Jack A. Mandelman, Donald C. Wheeler | 2001-06-26 |
| 6236077 | Trench electrode with intermediate conductive barrier layer | Rajarao Jammy, Jack A. Mandelman, Carl Radens | 2001-05-22 |
| 6232222 | Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure | Michael D. Armacost, Richard A. Conti, Jeremy K. Stephens | 2001-05-15 |
| 6222219 | Crown capacitor using a tapered etch of a damascene lower electrode | David E. Kotecki | 2001-04-24 |
| 6210995 | Method for manufacturing fusible links in a semiconductor device | Axel Brintzinger, Thomas Rupp, Scott D. Halle | 2001-04-03 |
| 6208008 | Integrated circuits having reduced stress in metallization | Kenneth C. Arndt, Richard A. Conti, David M. Dobuzinsky, Laertis Economikos, Peter D. Hoh +1 more | 2001-03-27 |
| 6204532 | Pillar transistor incorporating a body contact | Jack A. Mandelman, Stephen A. Parke, Matthew R. Wordeman | 2001-03-20 |
| 6201272 | Method for simultaneously forming a storage-capacitor electrode and interconnect | David E. Kotecki, Carl Radens, Gary B. Bronner | 2001-03-13 |
| 6200834 | Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP) planarization | Gary B. Bronner, Carl Radens | 2001-03-13 |
| 6194755 | Low-resistance salicide fill for trench capacitors | Ulrike Gruening, Jack A. Mandelman, Carl Radens | 2001-02-27 |
| 6177348 | Low temperature via fill using liquid phase transport | Peter D. Hoh, Mark A. Jaso, Ernest N. Levine | 2001-01-23 |
| 6174756 | Spacers to block deep junction implants and silicide formation in integrated circuits | Johann Alsmeier, Gary B. Bronner | 2001-01-16 |
| 6174762 | Salicide device with borderless contact | Gary B. Bronner, Louis L. Hsu, Jack A. Mandelman, Carl Radens, William R. Tonti | 2001-01-16 |
| 6166423 | Integrated circuit having a via and a capacitor | Mark A. Jaso, David E. Kotecki | 2000-12-26 |
| 6165896 | Self-aligned formation and method for semiconductors | Rainer Florian Schnabel, Zhijian Lu | 2000-12-26 |
| 6150212 | Shallow trench isolation method utilizing combination of spacer and fill | Ramachandra Divakaruni, Jack A. Mandelman, Carl Radens, William R. Tonti | 2000-11-21 |
| 6136655 | Method of making low voltage active body semiconductor device | Fariborz Assaderaghi, Claude L. Bertin, Louis L. Hsu, Jack A. Mandelman | 2000-10-24 |
| 6136686 | Fabrication of interconnects with two different thicknesses | Mark A. Jaso, Hing Wong | 2000-10-24 |
| 6124199 | Method for simultaneously forming a storage-capacitor electrode and interconnect | Gary B. Bronner, David E. Kotecki, Carl Radens | 2000-09-26 |
| 6114248 | Process to reduce localized polish stop erosion | Mark A. Jaso | 2000-09-05 |
| 6096664 | Method of manufacturing semiconductor structures including a pair of MOSFETs | Thomas Rupp, Stephan Kudelka, Mary E. Weybright | 2000-08-01 |
| 6090671 | Reduction of gate-induced drain leakage in semiconductor devices | Karanam Balasubramanyam, Martin Gall, Jack A. Mandelman | 2000-07-18 |
| 6084276 | Threshold voltage tailoring of corner of MOSFET device | Gary B. Bronner, Jack A. Mandelman, Larry Nesbit | 2000-07-04 |
| 6081021 | Conductor-insulator-conductor structure | Chandrasekhar Narayan, Toshiaki Kirihata | 2000-06-27 |
| 6060746 | Power transistor having vertical FETs and method for making same | Claude L. Bertin, Jack A. Mandelman | 2000-05-09 |