Issued Patents All Time
Showing 476–500 of 584 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7034400 | Dual damascene interconnect structure using low stress fluorosilicate insulator with copper conductors | Edward Barth, Glenn A. Biery, Thomas Ivers, Hyun Koo Lee, Ernest N. Levine +2 more | 2006-04-25 |
| 7015580 | Roughened bonding pad and bonding wire surfaces for low pressure wire bonding | John A. Fitzsimmons, Erick G. Walton | 2006-03-21 |
| 7015150 | Exposed pore sealing post patterning | Edward C. Cooney, III, John A. Fitzsimmons, Stephen E. Luce, Thomas L. McDevitt, Lee M. Nicholson +1 more | 2006-03-21 |
| 6989105 | Detection of hardmask removal using a selective etch | Anthony K. Stamper, Richard Wistrom | 2006-01-24 |
| 6960519 | Interconnect structure improvements | Timothy J. Dalton, John A. Fitzsimmons, Lee M. Nicholson, Andrew H. Simon, Anthony K. Stamper | 2005-11-01 |
| 6958540 | Dual damascene interconnect structures having different materials for line and via conductors | Edward C. Cooney, III, Anthony K. Stamper, William T. Motsiff, Michael Lane, Andrew H. Simon | 2005-10-25 |
| 6876028 | Metal-insulator-metal capacitor and method of fabrication | Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Vidhya Ramachandran | 2005-04-05 |
| 6838355 | Damascene interconnect structures including etchback for low-k dielectric materials | Anthony K. Stamper, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Lee M. Nicholson | 2005-01-04 |
| 6833720 | Electrical detection of dicing damage | Timothy H. Daubenspeck, Thomas L. McDevitt, Anthony K. Stamper | 2004-12-21 |
| 6827868 | Thinning of fuse passivation after C4 formation | Timothy H. Daubenspeck, William T. Motsiff | 2004-12-07 |
| 6809372 | Flash memory structure using sidewall floating gate | Louis L. Hsu, Jack A. Mandelman, Donald C. Wheeler | 2004-10-26 |
| 6797610 | Sublithographic patterning using microtrenching | Peter J. Lindgren, Anthony K. Stamper | 2004-09-28 |
| 6762108 | Method of forming a metal-insulator-metal capacitor for dual damascene interconnect processing and the device so formed | Stephen E. Luce, Thomas L. McDevitt, Henry W. Trombley | 2004-07-13 |
| 6734047 | Thinning of fuse passivation after C4 formation | Timothy H. Daubenspeck, William T. Motsiff | 2004-05-11 |
| 6720213 | Low-K gate spacers by fluorine implantation | Jack A. Mandelman, William R. Tonti | 2004-04-13 |
| 6689650 | Fin field effect transistor with self-aligned gate | Jerome B. Lasky, Jed H. Rankin | 2004-02-10 |
| 6674134 | Structure and method for dual gate oxidation for CMOS technology | Wayne S. Berry, Jack A. Mandelman, William R. Tonti | 2004-01-06 |
| 6670255 | Method of fabricating lateral diodes and bipolar transistors | James W. Adkisson, Peter B. Gray, Anthony K. Stamper | 2003-12-30 |
| 6590259 | Semiconductor device of an embedded DRAM on SOI substrate | James W. Adkisson, Ramachandra Divakaruni, Jack A. Mandelman | 2003-07-08 |
| 6548357 | Modified gate processing for optimized definition of array and logic devices on same chip | Mary E. Weybright, Gary B. Bronner, Richard A. Conti, Ramachandra Divakaruni, Peter D. Hoh +1 more | 2003-04-15 |
| 6538295 | Salicide device with borderless contact | Gary B. Bronner, Louis L. Hsu, Jack A. Mandelman, Carl Radens, William R. Tonti | 2003-03-25 |
| 6518670 | Electrically porous on-chip decoupling/shielding layer | Jack A. Mandelman, Ronald G. Filippi, Richard A. Wachnik | 2003-02-11 |
| 6518119 | Strap with intrinsically conductive barrier | Rajarao Jammy, Jack A. Mandelman, Carl Radens | 2003-02-11 |
| 6504210 | Fully encapsulated damascene gates for Gigabit DRAMs | Ramachandra Divakaruni, Jack A. Mandelman, Viraj Y. Sardesai, Mary E. Weybright | 2003-01-07 |
| 6504203 | Method of forming a metal-insulator-metal capacitor for dual damascene interconnect processing and the device so formed | Stephen E. Luce, Thomas L. McDevitt, Henry W. Trombley | 2003-01-07 |