Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7913347 | Rotational toothbrush | — | 2011-03-29 |
| 6327197 | Structure and method of a column redundancy memory | Juhan Kim | 2001-12-04 |
| 6288922 | Structure and method of an encoded ternary content addressable memory (CAM) cell for low-power compare operation | Subramani Kengeri | 2001-09-11 |
| 6262928 | Parallel test circuit and method for wide input/output DRAM | Juhan Kim | 2001-07-17 |
| 6236617 | High performance CMOS word-line driver | Louis L. Hsu, Hans-Oliver Joachim, Matthew R. Wordeman | 2001-05-22 |
| 6136686 | Fabrication of interconnects with two different thicknesses | Jeffrey P. Gambino, Mark A. Jaso | 2000-10-24 |
| 6115300 | Column redundancy based on column slices | Ali Massoumi | 2000-09-05 |
| 6069815 | Semiconductor memory having hierarchical bit line and/or word line architecture | Gerhard Mueller, Toshiaki Kirihata | 2000-05-30 |
| 5963489 | Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device | Toshiaki Kirihata, John K. DeBrosse, Yohji Watanabe | 1999-10-05 |
| 5903512 | Circuit and method to externally adjust internal circuit timing | Toshiaki Kirihata, Bozidar Krsnik | 1999-05-11 |
| 5848008 | Floating bitline test mode with digitally controllable bitline equalizers | Toshiaki Kirihata, Bozidar Krsnik | 1998-12-08 |
| 5804853 | Stacked electrical device having regions of electrical isolation and electrical connections on a given stack level | John Cronin, John K. DeBrosse | 1998-09-08 |
| 5745430 | Circuit and method to externally adjust internal circuit timing | Toshiaki Kirihata, Bozidar Krsnik | 1998-04-28 |
| 5741738 | Method of making corner protected shallow trench field effect transistor | Jack A. Mandelman, Brian J. Machesney, Michael M. Armacost, Pai-Hung Pan | 1998-04-21 |
| 5691946 | Row redundancy block architecture | John K. DeBrosse, Toshiaki Kirihata | 1997-11-25 |
| 5619460 | Method of testing a random access memory | Toshiaki Kirihata | 1997-04-08 |
| 5615164 | Latched row decoder for a random access memory | Toshiaki Kirihata | 1997-03-25 |
| 5610867 | DRAM signal margin test method | John K. DeBrosse, Toshiaki Kirihata | 1997-03-11 |
| 5602051 | Method of making stacked electrical device having regions of electrical isolation and electrical connection on a given stack level | John Cronin, John K. DeBrosse | 1997-02-11 |
| 5559739 | Dynamic random access memory with a simple test arrangement | John K. DeBrosse, Toshiaki Kirihata | 1996-09-24 |
| 5559050 | P-MOSFETS with enhanced anomalous narrow channel effect | Johann Alsmeier, Wayne F. Ellis, Jack A. Mandelman | 1996-09-24 |
| 5556802 | Method of making corrugated vertical stack capacitor (CVSTC) | Paul E. Bakeman, Jr., Bomy Chen, John Cronin, Steven J. Holmes | 1996-09-17 |
| 5521422 | Corner protected shallow trench isolation device | Jack A. Mandelman, Brian J. Machesney, Michael D. Armacost, Pai-Hung Pan | 1996-05-28 |
| 5517442 | Random access memory and an improved bus arrangement therefor | Toshiaki Kirihata, Yohji Watanabe | 1996-05-14 |
| 5276641 | Hybrid open folded sense amplifier architecture for a memory device | Edmund J. Sprogis | 1994-01-04 |