Issued Patents All Time
Showing 551–575 of 584 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6037648 | Semiconductor structure including a conductive fuse and process for fabrication thereof | Kenneth C. Arndt, Jack A. Mandelman, Chandrasekhar Narayan, Rainer Florian Schnabel, Ronald J. Schutz +1 more | 2000-03-14 |
| 6028004 | Process for controlling the height of a stud intersecting an interconnect | Gary B. Bronner | 2000-02-22 |
| 6025226 | Method of forming a capacitor and a capacitor formed using the method | Mark A. Jaso, David E. Kotecki | 2000-02-15 |
| 6020239 | Pillar transistor incorporating a body contact | Jack A. Mandelman, Stephen A. Parke, Matthew R. Wordeman | 2000-02-01 |
| 6015991 | Asymmetrical field effect transistor | Donald C. Wheeler, Louis L. Hsu, Jack A. Mandelman, Rebecca D. Mih | 2000-01-18 |
| 6014310 | High dielectric TiO.sub.2 -SiN composite films for memory applications | Gary B. Bronner, Stephan A. Cohen, David M. Dobuzinsky, Herbert L. Ho, Karen P. Madden | 2000-01-11 |
| 6013583 | Low temperature BPSG deposition process | Atul Ajmera, Son V. Nguyen | 2000-01-11 |
| 6004837 | Dual-gate SOI transistor | Jack A. Mandelman | 1999-12-21 |
| 5998847 | Low voltage active body semiconductor device | Fariborz Assaderaghi, Claude L. Bertin, Louis L. Hsu, Jack A. Mandelman | 1999-12-07 |
| 5994202 | Threshold voltage tailoring of the corner of a MOSFET device | Gary B. Bronner, Jack A. Mandelman, Larry Nesbit | 1999-11-30 |
| 5994215 | Method for suppression pattern distortion associated with BPSG reflow | Son V. Nguyen | 1999-11-30 |
| 5973385 | Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby | Son V. Nguyen, Reinhard Stengl | 1999-10-26 |
| 5960315 | Tapered via using sidewall spacer reflow | Carl Radens | 1999-09-28 |
| 5960318 | Borderless contact etch process with sidewall spacer and selective isotropic etch process | Matthias Peschke, James G. Ryan, Reinhard Stengl | 1999-09-28 |
| 5939335 | Method for reducing stress in the metallization of an integrated circuit | Kenneth C. Arndt, Richard A. Conti, David M. Dobuzinsky, Laertis Economikos, Peter D. Hoh +1 more | 1999-08-17 |
| 5937289 | Providing dual work function doping | Gary B. Bronner, Jack A. Mandelman, Carl Radens, William R. Tonti | 1999-08-10 |
| 5923991 | Methods to prevent divot formation in shallow trench isolation areas | Gary B. Bronner, Larry Nesbit | 1999-07-13 |
| 5915183 | Raised source/drain using recess etch of polysilicon | Scott D. Halle, Jack A. Mandelman, Jeremy K. Stephens | 1999-06-22 |
| 5882992 | Method for fabricating Tungsten local interconnections in high density CMOS circuits | Edward Kobeda, George G. Gifford, Nickolas Joseph Mazzeo | 1999-03-16 |
| 5879985 | Crown capacitor using a tapered etch of a damascene lower electrode | David E. Kotecki | 1999-03-09 |
| 5876788 | High dielectric TiO.sub.2 -SiN composite films for memory applications | Gary B. Bronner, Stephan A. Cohen, David M. Dobuzinsky, Herbert L. Ho, Karen P. Madden | 1999-03-02 |
| 5795826 | Method of chemically mechanically polishing an electronic component | Mark A. Jaso, Larry A. Nesbit | 1998-08-18 |
| 5792703 | Self-aligned contact wiring process for SI devices | Gary B. Bronner | 1998-08-11 |
| 5759867 | Method of making a disposable corner etch stop-spacer for borderless contacts | Michael D. Armacost | 1998-06-02 |
| 5622596 | High density selective SiO.sub.2 :Si.sub.3 N.sub.4 etching using a stoichiometrically altered nitride etch stop | Michael D. Armacost, David M. Dobuzinsky, Son V. Nguyen | 1997-04-22 |