Issued Patents All Time
Showing 176–200 of 888 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10957642 | Resistance tunable fuse structure formed by embedded thin metal layers | Alexander Reznicek, Miaomiao Wang, Donald F. Canaperi | 2021-03-23 |
| 10950662 | Resistive memory device with meshed electrodes | Takashi Ando, Lawrence A. Clevenger, Michael Rizzolo | 2021-03-16 |
| 10950493 | Interconnects having air gap spacers | Kenneth Chun Kuen Cheng, Koichi Motoyama, Oscar van der Straten, Joseph F. Maniscalco | 2021-03-16 |
| 10950459 | Back end of line structures with metal lines with alternating patterning and metallization schemes | Ruilong Xie, Chanro Park, Kangguo Cheng, Juntao Li | 2021-03-16 |
| 10950787 | Method having resistive memory crossbar array employing selective barrier layer growth | Takashi Ando, Lawrence A. Clevenger | 2021-03-16 |
| 10943972 | Precision BEOL resistors | Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Lawrence A. Clevenger, Junli Wang | 2021-03-09 |
| 10930589 | Advanced interconnects containing an IMT liner | Joseph F. Maniscalco, Andrew Tae Kim, Baozhen Li | 2021-02-23 |
| 10930520 | Self-formed liner for interconnect structures | — | 2021-02-23 |
| 10916699 | Resistive memory crossbar array employing selective barrier layer growth | Takashi Ando, Lawrence A. Clevenger | 2021-02-09 |
| 10916503 | Back end of line metallization structure | — | 2021-02-09 |
| 10916501 | Back end of line electrical fuse structure and method of fabrication | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo | 2021-02-09 |
| 10910307 | Back end of line metallization structure | Raghuveer R. Patlolla, James J. Kelly, Cornelius Brown Peethala | 2021-02-02 |
| 10903162 | Fuse element resistance enhancement by laser anneal and ion implantation | Liying Jiang, Juntao Li, Michael Rizzolo, Yi Song | 2021-01-26 |
| 10903161 | Back end of line metallization structure | Raghuveer R. Patlolla, James J. Kelly, Cornelius Brown Peethala | 2021-01-26 |
| 10903117 | Fabricating vias with lower resistance | Baozhen Li, Andrew Tae Kim | 2021-01-26 |
| 10903116 | Void-free metallic interconnect structures with self-formed diffusion barrier layers | Joseph F. Maniscalco, Koichi Motoyama, James J. Kelly, Hosadurga Shobha | 2021-01-26 |
| 10903115 | Controlling grain boundaries in high aspect-ratio conductive regions | Conal E. Murray | 2021-01-26 |
| 10901317 | Extreme ultraviolet (EUV) lithography patterning methods utilizing EUV resist hardening | Benjamin D. Briggs, Michael Rizzolo, Ekmini Anuja De Silva, Lawrence A. Clevenger | 2021-01-26 |
| 10896846 | Controlling performance and reliability of conductive regions in a metallization network | Raghuveer R. Patlolla, Cornelius Brown Peethala | 2021-01-19 |
| 10886166 | Dielectric surface modification in sub-40nm pitch interconnect patterning | Nicholas Anthony Lanzillo | 2021-01-05 |
| 10886168 | Surface modified dielectric refill structure | Terry A. Spooner, Koichi Motoyama, Shyng-Tsong Chen | 2021-01-05 |
| 10886225 | BEOL alternative metal interconnects: integration and process | Theo Standaert | 2021-01-05 |
| 10879190 | Patterning integration scheme with trench alignment marks | Hao Tang, Dominik Metzler, Cornelius Brown Peethala | 2020-12-29 |
| 10847458 | BEOL electrical fuse and method of forming the same | Baozhen Li | 2020-11-24 |
| 10847475 | Advanced crack stop structure | Baozhen Li, Xiao Hu Liu, Griselda Bonilla | 2020-11-24 |