Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
CY

Chih-Chao Yang — 888 Patents

IBM: 837 patents #5 of 70,183Top 1%
Globalfoundries: 21 patents #139 of 4,424Top 4%
ITITRI: 11 patents #451 of 9,619Top 5%
Infineon Technologies Ag: 8 patents #1,246 of 7,486Top 20%
TETessera: 7 patents #62 of 271Top 25%
UMUnited Microelectronics: 3 patents #1,523 of 4,560Top 35%
NLNational Applied Research Laboratories: 3 patents #58 of 506Top 15%
ETElpis Technologies: 2 patents #16 of 121Top 15%
NMNovatek Microelectronics: 1 patents #575 of 986Top 60%
CUClemson University: 1 patents #68 of 317Top 25%
GUGlobalfoundries U.S.: 1 patents #22 of 211Top 15%
Glenmont, NY: #1 of 67 inventorsTop 2%
New York: #4 of 115,490 inventorsTop 1%
Overall (All Time): #82 of 4,157,543Top 1%
888 Patents All Time

Issued Patents All Time

Showing 226–250 of 888 patents

Patent #TitleCo-InventorsDate
10756260 Co-fabrication of magnetic device structures with electrical interconnects having reduced resistance through increased conductor grain size Lawrence A. Clevenger, Liying Jiang, Sebastian Naczas, Michael Rizzolo 2020-08-25
10748812 Air-gap containing metal interconnects Kenneth Chun Kuen Cheng, Koichi Motoyama, Kisik Choi 2020-08-18
10741751 Fully aligned semiconductor device with a skip-level via Nicholas Anthony Lanzillo, Benjamin D. Briggs, Hsueh-Chung Chen, Lawrence A. Clevenger 2020-08-11
10741748 Back end of line metallization structures Joseph F. Maniscalco, Raghuveer R. Patlolla, Cornelius Brown Peethala 2020-08-11
10741609 Pre-patterned etch stop for interconnect trench formation overlying embedded MRAM structures Gangadhara Raja Muthinti, Michael Rizzolo, Oscar van der Straten 2020-08-11
10741441 Collar formation for chamfer-less and chamfered vias Baozhen Li, Andrew Tae Kim 2020-08-11
10741397 Liner planarization-free process flow for fabricating metallic interconnect structures 2020-08-11
10734579 Protuberant contacts for resistive switching devices Takashi Ando, Lawrence A. Clevenger 2020-08-04
10734277 Top via back end of the line interconnect integration Lawrence A. Clevenger, Benjamin D. Briggs, Brent A. Anderson 2020-08-04
10727123 Interconnect structure with fully self-aligned via pattern formation Kafai Lai 2020-07-28
10727070 Liner-less contact metallization Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten 2020-07-28
10714596 Directional deposition of protection layer Hong He, Juntao Li, Junli Wang 2020-07-14
10714382 Controlling performance and reliability of conductive regions in a metallization network Raghuveer R. Patlolla, Cornelius Brown Peethala 2020-07-14
10714379 Reducing contact resistance in vias for copper interconnects Conal E. Murray 2020-07-14
10707413 Formation of embedded magnetic random-access memory devices Ashim Dutta, John C. Arnold, Michael Rizzolo, Jon Slaughter 2020-07-07
10707166 Advanced metal interconnects 2020-07-07
10699945 Back end of line integration for interconnects Cornelius Brown Peethala, Raghuveer R. Patlolla, Roger A. Quon 2020-06-30
10699050 Front-end-of-line shape merging cell placement and optimization David Wolpert, Erwin Behnen, Lawrence A. Clevenger, Patrick Watson, Timothy A. Schell 2020-06-30
10692925 Dielectric fill for memory pillar elements Michael Rizzolo, Theodorus E. Standaert, Isabel Cristina Chu, Son V. Nguyen 2020-06-23
10692722 Single process for linear and metal fill Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten 2020-06-23
10686126 Back end of line metallization structures Joseph F. Maniscalco, Raghuveer R. Patlolla, Cornelius Brown Peethala 2020-06-16
10686124 Contact via structures Daniel C. Edelstein, Bruce B. Doris, Henry K. Utomo, Theodorus E. Standaert, Nathan P. Marchack 2020-06-16
10685915 Via contact resistance control Theodorus E. Standaert 2020-06-16
10685784 Back-end-of-the line capacitor 2020-06-16
10679892 Multi-buried ULK field in BEOL structure Yann Mignot, Hosadurga Shobha 2020-06-09