Issued Patents All Time
Showing 251–275 of 888 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10672707 | Low aspect ratio interconnect | Benjamin D. Briggs, Elbert E. Huang, Raghuveer R. Patlolla, Cornelius Brown Peethala, David L. Rath | 2020-06-02 |
| 10672653 | Metallic interconnect structures with wrap around capping layers | Cornelius Brown Peethala, Kedari Matam, Theo Standaert | 2020-06-02 |
| 10672649 | Advanced BEOL interconnect architecture | Theo Standaert | 2020-06-02 |
| 10672611 | Hardmask stress, grain, and structure engineering for advanced memory applications | Michael Rizzolo, Ashim Dutta, Oscar van der Straten | 2020-06-02 |
| 10658585 | Dedicated contacts for controlled electroforming of memory cells in resistive random-access memory array | Takashi Ando, Lawrence A. Clevenger, Benjamin D. Briggs | 2020-05-19 |
| 10658235 | Rework for metal interconnects using etch and thermal anneal | Prasad Bhosale, Terry A. Spooner, Lawrence A. Clevenger | 2020-05-19 |
| 10651083 | Graded interconnect cap | Andrew Tae Kim, Baozhen Li, Ernest Y. Wu | 2020-05-12 |
| 10643890 | Ultrathin multilayer metal alloy liner for nano Cu interconnects | Daniel C. Edelstein, Alfred Grill, Seth L. Knupp, Son V. Nguyen, Takeshi Nogami +2 more | 2020-05-05 |
| 10615119 | Back end of line electrical fuse structure and method of fabrication | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo | 2020-04-07 |
| 10615116 | Surface nitridation in metal interconnects | Lawrence A. Clevenger, Roger A. Quon, Terry A. Spooner, Wei Wang | 2020-04-07 |
| 10615112 | MIM capacitor for improved process defect tolerance | Baozhen Li, Andrew Tae Kim | 2020-04-07 |
| 10615074 | Advanced copper interconnects with hybrid microstructure | Daniel C. Edelstein | 2020-04-07 |
| 10600686 | Controlling grain boundaries in high aspect-ratio conductive regions | Conal E. Murray | 2020-03-24 |
| 10586732 | Via cleaning to reduce resistance | Yann Mignot | 2020-03-10 |
| 10585998 | Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance | Prasad Bhosale, Michael Rizzolo | 2020-03-10 |
| 10566314 | Microstructure modulation for metal wafer-wafer bonding | — | 2020-02-18 |
| 10559751 | Bottom electrode for semiconductor memory device | Theodorus E. Standaert, Daniel C. Edelstein | 2020-02-11 |
| 10559649 | Metal insulator metal capacitor with extended capacitor plates | Theodorus E. Standaert | 2020-02-11 |
| 10553789 | Fully aligned semiconductor device with a skip-level via | Nicholas Anthony Lanzillo, Benjamin D. Briggs, Hsueh-Chung Chen, Lawrence A. Clevenger | 2020-02-04 |
| 10553535 | Formation of semiconductor devices including electrically programmable fuses | Juntao Li | 2020-02-04 |
| 10553483 | Semiconductor device with reduced via resistance | Conal E. Murray | 2020-02-04 |
| 10546892 | Resistive memory device with meshed electrodes | Takashi Ando, Lawrence A. Clevenger, Michael Rizzolo | 2020-01-28 |
| 10546812 | Liner-free and partial liner-free contact/via structures | — | 2020-01-28 |
| 10541199 | BEOL integration with advanced interconnects | — | 2020-01-21 |
| 10534888 | Hybrid back end of line metallization to balance performance and reliability | Baozhen Li, Theo Standaert | 2020-01-14 |