Issued Patents All Time
Showing 126–150 of 888 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11164878 | Interconnect and memory structures having reduced topography variation formed in the BEOL | Baozhen Li, Raghuveer R. Patlolla, Cornelius Brown Peethala | 2021-11-02 |
| 11164779 | Bamboo tall via interconnect structures | Michael Rizzolo, Theodorus E. Standaert | 2021-11-02 |
| 11164774 | Interconnects with spacer structure for forming air-gaps | Kenneth Chun Kuen Cheng, Koichi Motoyama, Chanro Park | 2021-11-02 |
| 11158584 | Selective CVD alignment-mark topography assist for non-volatile memory | Michael Rizzolo, Lawrence A. Clevenger, Benjamin D. Briggs | 2021-10-26 |
| 11158786 | MRAM device formation with controlled ion beam etch of MTJ | Ashim Dutta, Lijuan Zou, John C. Arnold | 2021-10-26 |
| 11152300 | Electrical fuse with metal line migration | Baozhen Li, Yan Li, Keith Kwong Hon Wong | 2021-10-19 |
| 11145591 | Integrated circuit (IC) device integral capacitor and anti-fuse | Jim Shih-Chun Liang, Baozhen Li | 2021-10-12 |
| 11145813 | Bottom electrode for semiconductor memory device | Theodorus E. Standaert, Daniel C. Edelstein | 2021-10-12 |
| 11139202 | Fully aligned top vias with replacement metal lines | Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng | 2021-10-05 |
| 11139242 | Via-to-metal tip connections in multi-layer chips | Ruilong Xie, Chi-Chun Liu, Kangguo Cheng | 2021-10-05 |
| 11133457 | Controllable formation of recessed bottom electrode contact in a memory metallization stack | Raghuveer R. Patlolla, James J. Kelly | 2021-09-28 |
| 11133462 | Bottom electrode structure and method of forming the same | Baozhen Li, Andrew Tae Kim | 2021-09-28 |
| 11133216 | Interconnect structure | Hsueh-Chung Chen, Roger A. Quon | 2021-09-28 |
| 11127676 | Removal or reduction of chamfer for fully-aligned via | Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng | 2021-09-21 |
| 11121082 | Sub-ground rule e-Fuse structure | Andrew Tae Kim, Baozhen Li, Ernest Y. Wu | 2021-09-14 |
| 11107984 | Protuberant contacts for resistive switching devices | Takashi Ando, Lawrence A. Clevenger | 2021-08-31 |
| 11107731 | Self-aligned repaired top via | Ruilong Xie, Carl Radens, Juntao Li, Kangguo Cheng | 2021-08-31 |
| 11099230 | Electromigration test structures for void localization | Baozhen Li | 2021-08-24 |
| 11101175 | Tall trenches for via chamferless and self forming barrier | Yann Mignot, Hosadurga Shobha | 2021-08-24 |
| 11101213 | EFuse structure with multiple links | Baozhen Li, Jim Shih-Chun Liang, Tian Shen | 2021-08-24 |
| 11094527 | Wet clean solutions to prevent pattern collapse | Cornelius Brown Peethala, Raghuveer R. Patlolla, Hsueh-Chung Chen | 2021-08-17 |
| 11094580 | Structure and method to fabricate fully aligned via with reduced contact resistance | Chanro Park, Kenneth Chun Kuen Cheng, Koichi Motoyama | 2021-08-17 |
| 11094630 | Formation of semiconductor devices including electrically programmable fuses | Juntao Li | 2021-08-17 |
| 11087993 | Double replacement metal line patterning | Ruilong Xie, Kangguo Cheng, Hsueh-Chung Chen | 2021-08-10 |
| 11074387 | Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance | Prasad Bhosale, Michael Rizzolo | 2021-07-27 |