Issued Patents All Time
Showing 101–125 of 888 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11244853 | Fully aligned via interconnects with partially removed etch stop layer | Koichi Motoyama, Kenneth Chun Kuen Cheng, Chanro Park | 2022-02-08 |
| 11244850 | On integrated circuit (IC) device simultaneously formed capacitor and resistor | Jim Shih-Chun Liang, Baozhen Li | 2022-02-08 |
| 11239278 | Bottom conductive structure with a limited top contact area | Baozhen Li, Theodorus E. Standaert, Koichi Motoyama | 2022-02-01 |
| 11239165 | Method of forming an interconnect structure with enhanced corner connection | Ruilong Xie, Christopher J. Waskiewicz, Kangguo Cheng | 2022-02-01 |
| 11239160 | E-fuse with dielectric zipping | Tianji Zhou, Saumya Sharma, Ashim Dutta | 2022-02-01 |
| 11227997 | Planar resistive random-access memory (RRAM) device with a shared top electrode | Ashim Dutta, Saumya Sharma, Tianji Zhou | 2022-01-18 |
| 11227892 | MRAM integration with BEOL interconnect including top via | Ashim Dutta, Ekmini Anuja De Silva, Dominik Metzler | 2022-01-18 |
| 11227792 | Interconnect structures including self aligned vias | Terry A. Spooner, Koichi Motoyama, Shyng-Tsong Chen | 2022-01-18 |
| 11223655 | Semiconductor tool matching and manufacturing management in a blockchain | Prasad Bhosale, Nicholas Anthony Lanzillo, Michael Rizzolo | 2022-01-11 |
| 11222817 | Advanced copper interconnects with hybrid microstructure | Daniel C. Edelstein | 2022-01-11 |
| 11222815 | Semiconductor device with reduced via resistance | Conal E. Murray | 2022-01-11 |
| 11217742 | Bottom electrode for semiconductor memory device | Theodorus E. Standaert, Daniel C. Edelstein | 2022-01-04 |
| 11211291 | Via formation with robust hardmask removal | Ruilong Xie, Christopher J. Waskiewicz, Kangguo Cheng | 2021-12-28 |
| 11205591 | Top via interconnect with self-aligned barrier layer | Kenneth Chun Kuen Cheng, Chanro Park, Koichi Motoyama | 2021-12-21 |
| 11205592 | Self-aligned top via structure | Ruilong Xie, Cheng Chi, Kangguo Cheng | 2021-12-21 |
| 11205588 | Interconnect architecture with enhanced reliability | Baozhen Li, Naftali E. Lustig | 2021-12-21 |
| 11201056 | Pitch multiplication with high pattern fidelity | Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng | 2021-12-14 |
| 11201112 | Fully-aligned skip-vias | Kenneth Chun Kuen Cheng, Chanro Park, Koichi Motoyama | 2021-12-14 |
| 11195751 | Bilayer barrier for interconnect and memory structures formed in the BEOL | Baozhen Li | 2021-12-07 |
| 11177169 | Interconnects with gouged vias | Kenneth Chun Kuen Cheng, Koichi Motoyama, Hosadurga Shobha | 2021-11-16 |
| 11177163 | Top via structure with enlarged contact area with upper metallization level | Koichi Motoyama, Chanro Park, Kenneth Chun Kuen Cheng | 2021-11-16 |
| 11177167 | Ultrathin multilayer metal alloy liner for nano Cu interconnects | Daniel C. Edelstein, Alfred Grill, Seth L. Knupp, Son V. Nguyen, Takeshi Nogami +2 more | 2021-11-16 |
| 11177213 | Embedded small via anti-fuse device | Baozhen Li, Tianji Zhou, Ashim Dutta, Saumya Sharma | 2021-11-16 |
| 11177214 | Interconnects with hybrid metal conductors | Kenneth Chun Kuen Cheng, Chanro Park, Koichi Motoyama | 2021-11-16 |
| 11171044 | Planarization controllability for interconnect structures | Ruilong Xie, Chanro Park, Kangguo Cheng, Julien Frougier | 2021-11-09 |