Issued Patents All Time
Showing 451–475 of 633 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7759243 | Method for forming an on-chip high frequency electro-static discharge device | Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Xuefeng Liu | 2010-07-20 |
| 7741698 | Post last wiring level inductor using patterned plate process | Anil K. Chinthakindi, Douglas D. Coolbaugh, John E. Florkey, Jeffrey P. Gambino, Zhong-Xiang He +1 more | 2010-06-22 |
| 7741721 | Electrical fuses and resistors having sublithographic dimensions | Charles T. Black, Matthew E. Colburn, Timothy J. Dalton, Daniel C. Edelstein, Wai-Kin Li +1 more | 2010-06-22 |
| 7739632 | System and method of automated wire and via layout optimization description | Bette L. Bergman Reuter, Howard S. Landis, Jeanne-Tania Sucharitaves | 2010-06-15 |
| 7732295 | Post last wiring level inductor using patterned plate process | Anil K. Chinthakindi, Douglas D. Coolbaugh, John E. Florkey, Jeffrey P. Gambino, Zhong-Xiang He +1 more | 2010-06-08 |
| 7732294 | Post last wiring level inductor using patterned plate process | Anil K. Chinthakindi, Douglas D. Coolbaugh, John E. Florkey, Jeffrey P. Gambino, Zhong-Xiang He +1 more | 2010-06-08 |
| 7723178 | Shallow and deep trench isolation structures in semiconductor integrated circuits | James W. Adkisson, Andres Bryant, Mickey H. Yu | 2010-05-25 |
| 7713865 | Preventing damage to metal using clustered processing and at least partially sacrificial encapsulation | Jeffrey P. Gambino | 2010-05-11 |
| 7709905 | Dual damascene wiring and method | Thomas L. McDevitt | 2010-05-04 |
| 7704876 | Dual damascene interconnect structures having different materials for line and via conductors | Jeffrey P. Gambino, Edward C. Cooney, III, William T. Motsiff, Michael Lane, Andrew H. Simon | 2010-04-27 |
| 7700410 | Chip-in-slot interconnect for 3D chip stacks | Kerry Bernstein, Timothy J. Dalton, Edmund J. Sprogis, Richard Q. Williams | 2010-04-20 |
| 7678683 | Method of fabricating copper damascene and dual damascene interconnect wiring | Jeffrey P. Gambino, William R. Hill, Kenneth E. McAvey, Jr., Thomas L. McDevitt, Arthur C. Winslow +1 more | 2010-03-16 |
| 7674705 | Method of forming a semiconductor device | — | 2010-03-09 |
| 7670927 | Double-sided integrated circuit chips | Kerry Bernstein, Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Paul D. Kartschoke +1 more | 2010-03-02 |
| 7671442 | Air-gap insulated interconnections | Brent A. Anderson, Andres Bryant, Jeffrey P. Gambino | 2010-03-02 |
| 7670921 | Structure and method for self aligned vertical plate capacitor | Anil K. Chinthakindi, Douglas D. Coolbaugh, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino +1 more | 2010-03-02 |
| 7667328 | Integration circuits for reducing electromigration effect | Timothy D. Sullivan, Ping-Chuan Wang | 2010-02-23 |
| 7669170 | Circuit layout methodology using via shape process | John M. Cohn, Jason D. Hibbeler, Jed H. Rankin | 2010-02-23 |
| 7662722 | Air gap under on-chip passive device | Anil K. Chinthakindi, Douglas D. Coolbaugh, Timothy J. Dalton, Daniel C. Edelstein, Ebenezer E. Eshun +3 more | 2010-02-16 |
| 7659598 | Semiconductor ground shield | Mete Erturk, Alvin J. Joseph | 2010-02-09 |
| 7655547 | Metal spacer in single and dual damascene processing | Edward C. Cooney, III, Robert M. Geffken | 2010-02-02 |
| 7655495 | Damascene copper wiring optical image sensor | James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy | 2010-02-02 |
| 7645675 | Integrated parallel plate capacitors | Douglas D. Coolbaugh, Hanyi Ding, Ebenezer E. Eshun, Michael D. Gordon, Zhong-Xiang He | 2010-01-12 |
| 7602068 | Dual-damascene process to fabricate thick wire structure | Douglas D. Coolbaugh, Keith E. Downes, Peter J. Lindgren | 2009-10-13 |
| 7598166 | Dielectric layers for metal lines in semiconductor chips | Zhong-Xiang He, Ning Lu | 2009-10-06 |