Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7930667 | System and method of automated wire and via layout optimization description | Howard S. Landis, Anthony K. Stamper, Jeanne-Tania Sucharitaves | 2011-04-19 |
| 7739632 | System and method of automated wire and via layout optimization description | Howard S. Landis, Anthony K. Stamper, Jeanne-Tania Sucharitaves | 2010-06-15 |
| 7552417 | System for search and analysis of systematic defects in integrated circuits | David L. DeMaris, Mark A. Lavin, William C. Leipold, Daniel N. Maynard, Maharaj Mukherjee | 2009-06-23 |
| 7415695 | System for search and analysis of systematic defects in integrated circuits | David L. DeMaris, Mark A. Lavin, William C. Leipold, Daniel N. Maynard, Maharaj Mukherjee | 2008-08-19 |
| 7284230 | System for search and analysis of systematic defects in integrated circuits | David L. DeMaris, Mark A. Lavin, William C. Leipold, Daniel N. Maynard, Maharaj Mukherjee | 2007-10-16 |
| 6823496 | Physical design characterization system | Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds +1 more | 2004-11-23 |
| 6760901 | Trough adjusted optical proximity correction for vias | Eric M. Coker, William C. Leipold | 2004-07-06 |
| 6495917 | Method and structure of column interconnect | John J. Ellis-Monaghan, Paul M. Feeney, Robert M. Geffken, Howard S. Landis, Rosemary A. Previti-Kelly +3 more | 2002-12-17 |