Issued Patents All Time
Showing 426–450 of 633 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7930667 | System and method of automated wire and via layout optimization description | Bette L. Bergman Reuter, Howard S. Landis, Jeanne-Tania Sucharitaves | 2011-04-19 |
| 7928513 | Protection against charging damage in hybrid orientation transistors | Terence B. Hook, Anda C. Mocuta, Jeffrey W. Sleight | 2011-04-19 |
| 7915162 | Method of forming damascene filament wires | Brent A. Anderson, Andres Bryant, Jeffrey P. Gambino | 2011-03-29 |
| 7915158 | Method for forming an on-chip high frequency electro-static discharge device | Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Xuefeng Liu | 2011-03-29 |
| 7915134 | Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material | Anil K. Chinthakindi, Douglas D. Coolbaugh, Keith E. Downes, Ebenezer E. Eshun, Zhong-Xiang He +2 more | 2011-03-29 |
| 7910450 | Method of fabricating a precision buried resistor | Anil K. Chinthakindi, Douglas D. Coolbaugh, Keith E. Downes, Ebenezer E. Eshun, John E. Florkey +3 more | 2011-03-22 |
| 7902629 | Integrated BEOL thin film resistor | Anil K. Chinthakindi, Douglas D. Coolbaugh, John M. Cotte, Ebenezer E. Eshun, Zhong-Xiang He +1 more | 2011-03-08 |
| 7898063 | Through substrate annular via including plug filler | Peter J. Lindgren, Edmund J. Sprogis, Kenneth J. Stein | 2011-03-01 |
| 7892940 | Device and methodology for reducing effective dielectric constant in semiconductor devices | Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons +10 more | 2011-02-22 |
| 7879650 | Method of providing protection against charging damage in hybrid orientation transistors | Terence B. Hook, Anda C. Mocuta, Jeffrey W. Sleight | 2011-02-01 |
| 7863734 | Dual-sided chip attached modules | Kerry Bernstein, Timothy J. Dalton, Timothy H. Daubenspeck, Jeffrey P. Gambino, Mark D. Jaffe +3 more | 2011-01-04 |
| 7863180 | Through substrate via including variable sidewall profile | Edward C. Cooney, III, Peter J. Lindgren, Dorreen Jane Ossenkop | 2011-01-04 |
| 7861204 | Structures including integrated circuits for reducing electromigration effect | Timothy D. Sullivan, Ping-Chuan Wang | 2010-12-28 |
| 7859114 | IC chip and design structure with through wafer vias dishing correction | Peter J. Lindgren, Edmund J. Sprogis | 2010-12-28 |
| 7851923 | Low resistance and inductance backside through vias and methods of fabricating same | Mete Erturk, Robert A. Groves, Jeffrey B. Johnson, Alvin J. Joseph, Qizhi Liu +1 more | 2010-12-14 |
| 7847409 | Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner | Jeffrey P. Gambino | 2010-12-07 |
| 7833907 | CMP methods avoiding edge erosion and related wafer | Felix P. Anderson | 2010-11-16 |
| 7829452 | Terminal pad structures and methods of fabricating same | Douglas D. Coolbaugh, Daniel C. Edelstein, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel | 2010-11-09 |
| 7816738 | Low-cost FEOL for ultra-low power, near sub-vth device structures | Brent A. Anderson, Andres Bryant, William F. Clark, Jr., Jeffrey P. Gambino, Shih-Fen Huang +1 more | 2010-10-19 |
| 7803708 | Method for reducing amine based contaminants | Xiaomeng Chen, William J. Cote, Arthur C. Winslow | 2010-09-28 |
| 7804391 | Changing an electrical resistance of a resistor | Arne Ballantine, Cyril Cabral, Jr., Daniel C. Edelstein | 2010-09-28 |
| 7772028 | CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom | James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Richard J. Rassel | 2010-08-10 |
| 7768762 | Design structure for an on-chip high frequency electro-static discharge device | Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Xuefeng Liu | 2010-08-03 |
| 7768055 | Passive components in the back end of integrated circuits | Anil K. Chinthakindi, Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Jeffrey B. Johnson +2 more | 2010-08-03 |
| 7763954 | Post last wiring level inductor using patterned plate process | Anil K. Chinthakindi, Douglas D. Coolbaugh, John E. Florkey, Jeffrey P. Gambino, Zhong-Xiang He +1 more | 2010-07-27 |