Issued Patents All Time
Showing 26–50 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6794298 | CF4+H2O plasma ashing for reduction of contact/via resistance | Jeffrey A. Shields, Mohammad R. Rakhshandehroo | 2004-09-21 |
| 6784095 | Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing | Suzette K. Pangrle, Minh Van Ngo, Dawn Hopper | 2004-08-31 |
| 6773998 | Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning | Philip A. Fisher, Marina V. Plat, Chih-Yuh Yang, Christopher F. Lyons, Scott A. Bell +2 more | 2004-08-10 |
| 6764949 | Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication | Douglas J. Bonser, Marina V. Plat, Chih-Yuh Yang, Scott A. Bell, Darin A. Chan +6 more | 2004-07-20 |
| 6764947 | Method for reducing gate line deformation and reducing gate line widths in semiconductor devices | Darin A. Chan, Douglas J. Bonser, Marina V. Plat, Marilyn I. Wright, Chih-Yuh Yang +2 more | 2004-07-20 |
| 6756300 | Method for forming dual damascene interconnect structure | Fei Wang, Jerry Cheng, Lynne A. Okada, Minh Quoc Tran | 2004-06-29 |
| 6756672 | Use of sic for preventing copper contamination of low-k dielectric layers | Dawn Hopper, Suzette K. Pangrle | 2004-06-29 |
| 6750127 | Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance | Mark S. Chang, Darin A. Chan, Chih-Yuh Yang, Scott A. Bell, Srikanteswara Dakshina-Murthy +1 more | 2004-06-15 |
| 6724087 | Laminated conductive lines and methods of forming the same | Matthew S. Buynoski, Paul R. Besser, Sergey Lopatin | 2004-04-20 |
| 6713874 | Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics | Dawn Hopper, Minh Van Ngo | 2004-03-30 |
| 6699792 | Polymer spacers for creating small geometry space and method of manufacture thereof | Fei Wang, Lynne A. Okada | 2004-03-02 |
| 6689684 | Cu damascene interconnections using barrier/capping layer | Fei Wang, Richard J. Huang | 2004-02-10 |
| 6677679 | Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers | Fei Wang, Dawn Hopper | 2004-01-13 |
| 6663787 | Use of ta/tan for preventing copper contamination of low-k dielectric layers | Christy Mei-Chu Woo, Pin-Chin Connie Wang | 2003-12-16 |
| 6653735 | CVD silicon carbide layer as a BARC and hard mask for gate patterning | Chih-Yuh Yang, Douglas J. Bonser, Pei-Yuan Gao | 2003-11-25 |
| 6638358 | Method and system for processing a semiconductor device | Mark S. Chang, Hao Fang | 2003-10-28 |
| 6635943 | Method and system for reducing charge gain and charge loss in interlayer dielectric formation | Angela T. Hui, Tuan Pham, Richard J. Huang, Mark T. Ramsbey | 2003-10-21 |
| 6632707 | Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning | Fei Wang, Lynne A. Okada, Ramkumar Subramanian, James Kai, Calvin T. Gabriel | 2003-10-14 |
| 6627973 | Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device | Minh Van Ngo, Robert A. Huertas, King Wai Kelwin Ko, Pei-Yuan Gao | 2003-09-30 |
| 6596631 | Method of forming copper interconnect capping layers with improved interface and adhesion | Minh Van Ngo, Hartmut Ruelke, Lothar Mergili, Joerg Hohage, Robert A. Huertas +1 more | 2003-07-22 |
| 6586842 | Dual damascene integration scheme for preventing copper contamination of dielectric layer | Fei Wang, Christy Mei-Chu Woo | 2003-07-01 |
| 6576982 | Use of sion for preventing copper contamination of dielectric layer | Dawn Hopper, Minh Van Ngo | 2003-06-10 |
| 6576545 | Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers | Dawn Hopper, Minh Van Ngo | 2003-06-10 |
| 6577009 | Use of sic for preventing copper contamination of dielectric layer | Fei Wang, Minh Van Ngo | 2003-06-10 |
| 6573179 | Forming a strong interface between interconnect and encapsulation to minimize electromigration | Pin-Chin Connie Wang | 2003-06-03 |