Issued Patents All Time
Showing 26–50 of 135 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11257714 | Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same | Yi-Wen Wu, Chun-Chieh Wang, Chung-Shi Liu | 2022-02-22 |
| 11233032 | Mechanisms for forming bonding structures | Yeong-Jyh Lin, Hsin-Hung Liao, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu | 2022-01-25 |
| 11217555 | Aligning bumps in fan-out packaging process | Ying-Jui Huang, Chih-Wei Lin, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu | 2022-01-04 |
| 11139177 | Method of fabricating semiconductor package structure | Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang | 2021-10-05 |
| 11133274 | Fan-out interconnect structure and method for forming same | Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu +2 more | 2021-09-28 |
| 11101232 | Conductive micro pin | Ying-Jui Huang, Chung-Shi Liu, Hsin-Hung Liao | 2021-08-24 |
| 11094561 | Semiconductor package structure | Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang | 2021-08-17 |
| 11075439 | Electronic device and manufacturing method thereof | Pei-Hsuan Lee, Ching-Hua Hsieh, Yu-Ting Chiu, Jui-Chang Kuo | 2021-07-27 |
| 11024618 | Wafer-level underfill and over-molding | Bor-Ping Jang, Chung-Shi Liu, Yeong-Jyh Lin | 2021-06-01 |
| 11004758 | Integrated circuit package and method | Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee +3 more | 2021-05-11 |
| 10985135 | Methods for controlling warpage in packaging | Bor-Ping Jang, Jen-Chun Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu | 2021-04-20 |
| 10879197 | Package structure and method of fabricating package structure | Albert Wan, Chung-Shi Liu, Chao-Wen Shih, Han-Ping Pu | 2020-12-29 |
| 10867878 | Dam for three-dimensional integrated circuit | Tsung-Ding Wang, An-Jhih Su, Jung Wei Cheng, Hsin-Yu Pan, Chen-Hua Yu | 2020-12-15 |
| 10867832 | Apparatus for holding semiconductor wafers | Chen-Hua Yu | 2020-12-15 |
| 10867890 | Mutli-chip package with encapsulated conductor via | Ching-Hua Hsieh, Hsin-Hung Liao, Sung-Yueh Wu | 2020-12-15 |
| 10804234 | Semiconductor device having a boundary structure, a package on package structure, and a method of making | Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang | 2020-10-13 |
| 10770331 | Semiconductor wafer device and manufacturing method thereof | Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin | 2020-09-08 |
| 10756052 | Method of manufacturing integrated fan-out package | Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih +5 more | 2020-08-25 |
| 10734345 | Packaging through pre-formed metal pins | Chen-Hua Yu, Yeong-Jyh Lin | 2020-08-04 |
| 10734341 | Via structure for packaging and a method of forming | Ming-Che Ho, Yi-Wen Wu, Hung-Jui Kuo, Chung-Shi Liu | 2020-08-04 |
| 10727074 | Method and system for thinning wafer thereof | Bor-Ping Jang, Hsin-Hung Liao, Chung-Shi Liu | 2020-07-28 |
| 10700025 | Fan-out interconnect structure and method for forming same | Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu +2 more | 2020-06-30 |
| 10679866 | Interconnect structure for semiconductor package and method of fabricating the interconnect structure | Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang | 2020-06-09 |
| 10665537 | Package structure and manufacturing method thereof | Chun-Lin Lu, Kai-Chiang Wu | 2020-05-26 |
| 10513070 | Wafer level transfer molding and apparatus for performing the same | Bor-Ping Jang, Yeong-Jyh Lin, Chung-Shi Liu, Meng-Tse Chen, Ming-Da Cheng +1 more | 2019-12-24 |