Issued Patents All Time
Showing 26–50 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11462536 | Integrated circuit structures having asymmetric source and drain structures | Anupama Bowonder, Rishabh Mehandru, Tahir Ghani | 2022-10-04 |
| 11437514 | Semiconductor device having tipless epitaxial source/drain regions | — | 2022-09-06 |
| 11410928 | Device layer interconnects | Mauro J. Kobrinsky, Marni Nabors | 2022-08-09 |
| 11387198 | Device, system and method for providing inductor structures | Wilfred Gomes, Doug B. Ingerly, Rajesh Kumar, Harish Krishnamurthy, Nachiket Desai | 2022-07-12 |
| 11373999 | Deep trench via for three-dimensional integrated circuit | Yih Wang, Rishabh Mehandru, Mauro J. Kobrinsky, Tahir Ghani, Marni Nabors | 2022-06-28 |
| 11373987 | Device, method and system for providing a stacked arrangement of integrated circuit dies | Wilfred Gomes, Glenn J. Hinton, Rajesh Kumar | 2022-06-28 |
| 11271010 | Multi version library cell handling and integrated circuit structures fabricated therefrom | Ranjith Kumar, Quan Shi, Andrew W. Yeoh, Sourav Chakravarty, Barbara A. Chappell +1 more | 2022-03-08 |
| 11257804 | Distributed semiconductor die and package architecture | Wilfred Gomes, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. Mc Cullough | 2022-02-22 |
| 11249113 | High density and fine pitch interconnect structures in an electric test apparatus | Pooya Tadayon, Joe Walczyk | 2022-02-15 |
| 11222863 | Techniques for die stacking and associated configurations | Fay Hua, Christopher M. Pelto, Valluri Rao, Johanna M. Swan | 2022-01-11 |
| 11201129 | Designs and methods for conductive bumps | Valery M. Dubin, Sridhar Balakrishnan | 2021-12-14 |
| 11139241 | Integrated circuit device with crenellated metal trace layout | Patrick Morrow, Mauro J. Kobrinsky, Tahir Ghani, Rishabh Mehandru, Ranjith Kumar | 2021-10-05 |
| 11127712 | Functionally redundant semiconductor dies and package | Wilfred Gomes, Udi Sherel, Leonard NEIBERG, Nevine Nassif, Wesley McCullough | 2021-09-21 |
| 11068640 | Power shared cell architecture | Ranjith Kumar, Ruth A. Brain, Marni Nabors, Tai-Hsuan Wu, Sourav Chakravarty | 2021-07-20 |
| 11043459 | Multiple reticle field semiconductor devices | Edward A. Burton, Murray Fitzpatrick Kelley, Shawn Michael Klauser | 2021-06-22 |
| 11037923 | Through gate fin isolation | Stephen M. Cea, Barbara A. Chappell | 2021-06-15 |
| 11024601 | Hyperchip | Wilfred Gomes, Rajesh Kumar, Pooya Tadayon, Doug B. Ingerly | 2021-06-01 |
| 11004739 | Gate contact structure over active gate and method to fabricate same | Abhijit Jayant Pethe, Tahir Ghani, Clair Webb, Harry Gomez, Annalisa Cappellani | 2021-05-11 |
| 10930557 | Self-aligned contacts | Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2021-02-23 |
| 10892215 | Metal on both sides with power distributed through the silicon | Donald W. Nelson, Patrick Morrow | 2021-01-12 |
| 10886217 | Integrated circuit device with back-side interconnection to deep source/drain semiconductor | Patrick Morrow, Mauro J. Kobrinsky, Tahir Ghani, Rishabh Mehandru | 2021-01-05 |
| 10877068 | High density and fine pitch interconnect structures in an electric test apparatus | Pooya Tadayon, Joe Walczyk | 2020-12-29 |
| 10790354 | Self-aligned gate edge and local interconnect | Milton Clair Webb, Tahir Ghani, Szuya S. Liao | 2020-09-29 |
| 10770587 | Semiconductor device having tipless epitaxial source/drain regions | — | 2020-09-08 |
| 10685947 | Distributed semiconductor die and package architecture | Wilfred Gomes, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. Mc Cullough | 2020-06-16 |