Issued Patents All Time
Showing 51–75 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10672650 | Via blocking layer | Rami Hourani, Marie Krysak, Florian Gstrein, Ruth A. Brain | 2020-06-02 |
| 10629483 | Self-aligned contacts | Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2020-04-21 |
| 10535601 | Via blocking layer | Rami Hourani, Marie Krysak, Florian Gstrein, Ruth A. Brain, Manish Chandhok | 2020-01-14 |
| 10488438 | High density and fine pitch interconnect structures in an electric test apparatus | Pooya Tadayon, Joe Walczyk | 2019-11-26 |
| 10490662 | Semiconductor device having tipless epitaxial source/drain regions | — | 2019-11-26 |
| 10325840 | Metal on both sides with power distributed through the silicon | Donald W. Nelson, Patrick Morrow | 2019-06-18 |
| 10319812 | Self-aligned gate edge and local interconnect and method to fabricate same | Milton Clair Webb, Tahir Ghani, Szuya S. Liao | 2019-06-11 |
| 10249588 | Designs and methods for conductive bumps | Valery M. Dubin, Sridhar Balakrishnan | 2019-04-02 |
| 10192783 | Gate contact structure over active gate and method to fabricate same | Abhijit Jayant Pethe, Tahir Ghani, Clair Webb, Harry Gomez, Annalisa Cappellani | 2019-01-29 |
| 10141442 | Semiconductor device having tipless epitaxial source/drain regions | — | 2018-11-27 |
| 10141226 | Self-aligned contacts | Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2018-11-27 |
| 9899255 | Via blocking layer | Rami Hourani, Marie Krysak, Florian Gstrein, Ruth A. Brain | 2018-02-20 |
| 9892967 | Self-aligned contacts | Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2018-02-13 |
| 9831306 | Self-aligned gate edge and local interconnect and method to fabricate same | Milton Clair Webb, Tahir Ghani, Szuya S. Liao | 2017-11-28 |
| 9646890 | Replacement metal gates to enhance transistor strain | — | 2017-05-09 |
| 9543261 | Designs and methods for conductive bumps | Valery M. Dubin, Sridhar Balakrishnan | 2017-01-10 |
| 9530740 | 3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach | Kevin J. Lee, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju +1 more | 2016-12-27 |
| 9508821 | Self-aligned contacts | Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2016-11-29 |
| 9466565 | Self-aligned contacts | Tahir Ghani, Nadia M. Rahhai-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2016-10-11 |
| 9461143 | Gate contact structure over active gate and method to fabricate same | Abhijit Jayant Pethe, Tahir Ghani, Clair Webb, Harry Gomez, Annalisa Cappellani | 2016-10-04 |
| 9449913 | 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias | Kevin J. Lee, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju +1 more | 2016-09-20 |
| 9391013 | 3D integrated circuit package with window interposer | Debendra Mallik, Ram Viswanath, Sriram Srinivasan, Andrew W. Yeoh, Sairam Agraharam | 2016-07-12 |
| 9337336 | Replacement metal gates to enhance tranistor strain | — | 2016-05-10 |
| 9276112 | Semiconductor device having tipless epitaxial source/drain regions | — | 2016-03-01 |
| 9159566 | Replacement metal gates to enhance transistor strain | — | 2015-10-13 |