Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11158558 | Package with underfill containment barrier | Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun Kane Jen, Vipul V. Mehta +4 more | 2021-10-26 |
| 11114353 | Hybrid microelectronic substrates | Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard C. Stamey | 2021-09-07 |
| 11107780 | Pseudo-stripline using double solder-resist structure | Lilia May, Robert Alan May, Robert L. Sankman | 2021-08-31 |
| 11075130 | Package substrate having polymer-derived ceramic core | Lisa Ying Ying Chen, Lauren A. Link, Robert Alan May, Kristof Darmawikarta, Siddharth K. Alur +3 more | 2021-07-27 |
| 11043457 | Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same | Sri Ranga Sai Boyapati, Robert Alan May, Islam A. Salama, Robert L. Sankman | 2021-06-22 |
| 10998262 | Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge | Jiun Hann Sir, Poh Boon Khoo, Eng Huat Goh, Debendra Mallik | 2021-05-04 |
| 10980129 | Asymmetric electronic substrate and method of manufacture | Sri Chaitra Jyotsna Chavali, Wei-Lun Kane Jen, Sriram Srinivasan | 2021-04-13 |
| 10741947 | Plated through hole socketing coupled to a solder ball to engage with a pin | Siddharth K. Alur, Liwei Cheng, Lauren A. Link, Jonathan L. Rosch, Sai Vadlamani +1 more | 2020-08-11 |
| 10734358 | Multi-packaging for single-socketing | Jonathan L. Rosch, Arun Chandrasekhar, Shawna M. Liff | 2020-08-04 |
| 10707168 | Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same | Sri Ranga Sai Boyapati, Robert Alan May, Islam A. Salama, Robert L. Sankman | 2020-07-07 |
| 10624213 | Asymmetric electronic substrate and method of manufacture | Sri Chaitra Jyotsna Chavali, Wei-Lun Kane Jen, Sriram Srinivasan | 2020-04-14 |
| 10494700 | Method of fabricating a microelectronic substrate | Robert Alan May, Sri Ranga Sai Boyapati, Daniel N. Sobieski | 2019-12-03 |
| 10163798 | Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same | Sri Ranga Sai Boyapati, Robert Alan May, Islam A. Salama, Robert L. Sankman | 2018-12-25 |
| 9953959 | Metal protected fan-out cavity | Kristof Darmawikarta, Robert Alan May, Yikang Deng, Sheng Li, Chong Zhang +2 more | 2018-04-24 |
| 9758845 | Microelectronic substrates having copper alloy conductive route structures | Robert Alan May, Sri Ranga Sai Boyapati, Daniel N. Sobieski | 2017-09-12 |
| 9603247 | Electronic package with narrow-factor via including finish layer | Rajasekaran Swaminathan, Sairam Agraharam, Ram Viswanath, Wei-Lun Kane Jen | 2017-03-21 |
| 8456016 | Method and core materials for semiconductor packaging | Yonggang Li, Devarajan Balaraman, Xiwang Qi, Charan Gurumurthy | 2013-06-04 |
| 8142878 | Heat resistant halogen free substrate core material | Omar J. Bchir | 2012-03-27 |
| 7909977 | Method of manufacturing a substrate for a microelectronic device, and substrate formed thereby | Houssam Jomaa, Dilan Seneviratne | 2011-03-22 |
| 7749900 | Method and core materials for semiconductor packaging | Yonggang Li, Devarajan Balaraman, Xiwang Qi, Charan Gurumurthy | 2010-07-06 |