SA

Siddharth K. Alur

IN Intel: 21 patents #1,904 of 30,777Top 7%
Overall (All Time): #188,199 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12334447 Lithographically defined vertical interconnect access (VIA) for a bridge die first level interconnect (FLI) Kristof Darmawikarta, Tarek A. Ibrahim, Rahul Jain, Haobo Chen 2025-06-17
12327773 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Wei-Lun Kane Jen, Vipul V. Mehta, Ashish Dhall +4 more 2025-06-10
12224253 Magnetic inductor device and method Xin Ning, Brandon C. Marin, Kyu Oh Lee, Numair Ahmed, Brent Williams +3 more 2025-02-11
12062551 High density organic interconnect structures Sri Chaitra Jyotsna Chavali, Lilia May, Amanda E. Schuckman 2024-08-13
11935805 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Wei-Lun Kane Jen, Vipul V. Mehta, Ashish Dhall +4 more 2024-03-19
11664290 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Wei-Lun Kane Jen, Vipul V. Mehta, Ashish Dhall +4 more 2023-05-30
11631595 High density organic interconnect structures Sri Chaitra Jyotsna Chavali, Lilia May, Amanda E. Schuckman 2023-04-18
11508636 Multi-layer solution based deposition of dielectrics for advanced substrate architectures Andrew J. Brown, Ji-Yong Park, Cheng Xu, Amruthavalli Pallavi Alur 2022-11-22
11393762 Formation of tall metal pillars using multiple photoresist layers Sri Chaitra Jyotsna Chavali, Liwei Cheng, Sheng Li 2022-07-19
11195727 High density organic interconnect structures Sri Chaitra Jyotsna Chavali, Lilia May, Amanda E. Schuckman 2021-12-07
11196165 Low z-height, ultra-low dielectric constant air cavity based and multi-core/highly asymmetric antenna substrate architectures for electrical performance improvements in 5G mm-wave applications Sri Chaitra Jyotsna Chavali, Sheng Li 2021-12-07
11158558 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Wei-Lun Kane Jen, Vipul V. Mehta, Ashish Dhall +4 more 2021-10-26
11075130 Package substrate having polymer-derived ceramic core Lisa Ying Ying Chen, Lauren A. Link, Robert Alan May, Amruthavalli Pallavi Alur, Kristof Darmawikarta +3 more 2021-07-27
10903137 Electrical interconnections with improved compliance due to stress relaxation and method of making Sri Chaitra Jyotsna Chavali 2021-01-26
10741947 Plated through hole socketing coupled to a solder ball to engage with a pin Amruthavalli Pallavi Alur, Liwei Cheng, Lauren A. Link, Jonathan L. Rosch, Sai Vadlamani +1 more 2020-08-11
10727184 Microelectronic device including non-homogeneous build-up dielectric Srinivas V. Pietambaram 2020-07-28
10685850 High density organic interconnect structures Sri Chaitra Jyotsna Chavali, Lilia May, Amanda E. Schuckman 2020-06-16
10553453 Systems and methods for semiconductor packages using photoimageable layers Sri Chaitra Jyotsna Chavali, Amanda E. Schuckman, Amruthavalli P. Alur, Islam A. Salama, Yikang Deng +1 more 2020-02-04
10424530 Electrical interconnections with improved compliance due to stress relaxation and method of making Sri Chaitra Jyotsna Chavali 2019-09-24
10384431 Methods for forming a substrate structure for an electrical component and an apparatus for applying pressure to an electrically insulating laminate located on a core substrate Ji-Yong Park, Sri Chaitra Jyotsna Chavali, Kyu Oh Lee 2019-08-20
10020262 High resolution solder resist material for silicon bridge application Sheng Li, Wei-Lun Kane Jen 2018-07-10
9728500 Integrated circuit surface layer with adhesion-functional group Sri Chaitra Jyotsna Chavali, Robert Alan May, Whitney Bryks 2017-08-08