Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Siddharth K. Alur — 22 Patents

Intel: 21 patents #1,927 of 30,777Top 7%
Chandler, AZ: #241 of 3,331 inventorsTop 8%
Arizona: #1,496 of 32,909 inventorsTop 5%
Overall (All Time): #189,202 of 4,157,543Top 5%
22 Patents All Time
Siddharth K. Alur has been granted 22 US patents while listed as an inventor at Intel. The first was granted in 2017 and the most recent in June 2025. Siddharth K. Alur ranks #189,202 of 4,157,543 US inventors in our database (top 4.6%). Patent records list Siddharth K. Alur in Chandler, AZ, US.

Patents per Year

Patents granted per year, 2017 to 2025Bar chart with a peak of 5 patents in 2021.peak 52017: 1 patents20172018: 1 patents20182019: 2 patents20192020: 4 patents20202021: 5 patents20212022: 2 patents20222023: 2 patents20232024: 2 patents20242025: 3 patents2025

Issued Patents All Time

Showing 1–22 of 22 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12334447 Lithographically defined vertical interconnect access (VIA) for a bridge die first level interconnect (FLI) Kristof Darmawikarta, Tarek A. Ibrahim, Rahul Jain, Haobo Chen 2025-06-17
12327773 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Wei-Lun Kane Jen, Vipul V. Mehta, Ashish Dhall +4 more 2025-06-10
12224253 Magnetic inductor device and method Xin Ning, Brandon C. Marin, Kyu Oh Lee, Numair Ahmed, Brent Williams +3 more 2025-02-11
12062551 High density organic interconnect structures Sri Chaitra Jyotsna Chavali, Lilia May, Amanda E. Schuckman 2024-08-13 $26,861,000
11935805 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Wei-Lun Kane Jen, Vipul V. Mehta, Ashish Dhall +4 more 2024-03-19 $28,784,000
11664290 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Wei-Lun Kane Jen, Vipul V. Mehta, Ashish Dhall +4 more 2023-05-30 $16,378,000
11631595 High density organic interconnect structures Sri Chaitra Jyotsna Chavali, Lilia May, Amanda E. Schuckman 2023-04-18 $32,873,000
11508636 Multi-layer solution based deposition of dielectrics for advanced substrate architectures Andrew J. Brown, Ji-Yong Park, Cheng Xu, Amruthavalli Pallavi Alur 2022-11-22 $12,862,000
11393762 Formation of tall metal pillars using multiple photoresist layers Sri Chaitra Jyotsna Chavali, Liwei Cheng, Sheng Li 2022-07-19 $11,394,000
11196165 Low z-height, ultra-low dielectric constant air cavity based and multi-core/highly asymmetric antenna substrate architectures for electrical performance improvements in 5G mm-wave applications Sri Chaitra Jyotsna Chavali, Sheng Li 2021-12-07 $28,128,000
11195727 High density organic interconnect structures Sri Chaitra Jyotsna Chavali, Lilia May, Amanda E. Schuckman 2021-12-07 $28,128,000
11158558 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Wei-Lun Kane Jen, Vipul V. Mehta, Ashish Dhall +4 more 2021-10-26 $21,268,000
11075130 Package substrate having polymer-derived ceramic core Lisa Ying Ying Chen, Lauren A. Link, Robert Alan May, Amruthavalli Pallavi Alur, Kristof Darmawikarta +3 more 2021-07-27 $27,337,000
10903137 Electrical interconnections with improved compliance due to stress relaxation and method of making Sri Chaitra Jyotsna Chavali 2021-01-26 $50,999,000
10741947 Plated through hole socketing coupled to a solder ball to engage with a pin Amruthavalli Pallavi Alur, Liwei Cheng, Lauren A. Link, Jonathan L. Rosch, Sai Vadlamani +1 more 2020-08-11 $37,011,000
10727184 Microelectronic device including non-homogeneous build-up dielectric Srinivas V. Pietambaram 2020-07-28 $26,273,000
10685850 High density organic interconnect structures Sri Chaitra Jyotsna Chavali, Lilia May, Amanda E. Schuckman 2020-06-16 $36,850,000
10553453 Systems and methods for semiconductor packages using photoimageable layers Sri Chaitra Jyotsna Chavali, Amanda E. Schuckman, Amruthavalli P. Alur, Islam A. Salama, Yikang Deng +1 more 2020-02-04 $21,361,000
10424530 Electrical interconnections with improved compliance due to stress relaxation and method of making Sri Chaitra Jyotsna Chavali 2019-09-24 $28,939,000
10384431 Methods for forming a substrate structure for an electrical component and an apparatus for applying pressure to an electrically insulating laminate located on a core substrate Ji-Yong Park, Sri Chaitra Jyotsna Chavali, Kyu Oh Lee 2019-08-20 $17,708,000
10020262 High resolution solder resist material for silicon bridge application Sheng Li, Wei-Lun Kane Jen 2018-07-10 $30,438,000
9728500 Integrated circuit surface layer with adhesion-functional group Sri Chaitra Jyotsna Chavali, Robert Alan May, Whitney Bryks 2017-08-08 $11,912,000