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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
VM

Vipul V. Mehta — 19 Patents

Intel: 19 patents #2,167 of 30,777Top 8%
Chandler, AZ: #296 of 3,331 inventorsTop 9%
Arizona: #1,803 of 32,909 inventorsTop 6%
Overall (All Time): #229,345 of 4,157,543Top 6%
19 Patents All Time
Vipul V. Mehta has been granted 19 US patents while listed as an inventor at Intel. The first was granted in 2014 and the most recent in July 2025. Vipul V. Mehta ranks #229,345 of 4,157,543 US inventors in our database (top 5.5%). Patent records list Vipul V. Mehta in Chandler, AZ, US.

Patents per Year

Patents granted per year, 2014 to 2025Bar chart with a peak of 6 patents in 2023.peak 62014: 1 patents20142019: 3 patents20192021: 2 patents20212022: 1 patents20222023: 6 patents20232024: 4 patents20242025: 2 patents2025

Issued Patents All Time

Showing 1–19 of 19 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12362250 Protruding SN substrate features for epoxy flow control Edvin Cetegen, Jacob VEHONSKY, Nicholas S. Haehn, Thomas HEATON, Steve Cho +5 more 2025-07-15
12327773 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun Kane Jen, Ashish Dhall +4 more 2025-06-10
12130482 Hydrophobic feature to control adhesive flow Bassam M. Ziadeh, Jingyi Huang, Yiqun Bai, Ziyin Lin, Joseph Van Nausdle 2024-10-29 $18,861,000
12009271 Protruding SN substrate features for epoxy flow control Edvin Cetegen, Jacob VEHONSKY, Nicholas S. Haehn, Thomas HEATON, Steve Cho +5 more 2024-06-11 $21,221,000
12002727 Barrier structures for underfill containment Ziyin Lin, Wei Li, Edvin Cetegen, Xavier Francois Brun, Yang Guo +6 more 2024-06-04 $24,500,000
11935805 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun Kane Jen, Ashish Dhall +4 more 2024-03-19 $28,784,000
11776821 Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap Ziyin Lin, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan +1 more 2023-10-03 $24,984,000
11749585 High thermal conductivity, high modulus structure within a mold material layer of an integrated circuit package Yiqun Bai, John C. DECKER, Ziyin Lin 2023-09-05 $19,899,000
11688634 Trenches in wafer level packages for improvements in warpage reliability and thermals Yiqun Bai, Ziyin Lin, John C. DECKER, Yan Li 2023-06-27 $18,721,000
11676876 Semiconductor die package with warpage management and process for forming such Ziyin Lin, Elizabeth Nofen, Taylor Gaines 2023-06-13 $22,204,000
11664290 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun Kane Jen, Ashish Dhall +4 more 2023-05-30 $16,378,000
11545441 Semiconductor package having wafer-level active die and external die mount Eric J. Li, Sanka Ganesan, Debendra Mallik, Robert L. Sankman 2023-01-03 $15,575,000
11282717 Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap Ziyin Lin, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan +1 more 2022-03-22 $16,833,000
11158558 Package with underfill containment barrier Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun Kane Jen, Ashish Dhall +4 more 2021-10-26 $21,268,000
10910317 Semiconductor package having wafer-level active die and external die mount Eric J. Li, Sanka Ganesan, Debendra Mallik, Robert L. Sankman 2021-02-02 $28,243,000
10403578 Electronic device package Digvijay A. Raorane 2019-09-03 $18,715,000
10373888 Electronic package assembly with compact die placement Eric J. Li, Digvijay A. Raorane 2019-08-06 $15,127,000
10290592 Semiconductor package, and a method for forming a semiconductor package John J. Beatty, Suzana Prstic 2019-05-14 $24,469,000
8895365 Techniques and configurations for surface treatment of an integrated circuit substrate Suriyakala Ramalingam, Rajen S. Sidhu, Nisha Ananthakrishnan, Sivakumar Nagarajan, Wei Tan +1 more 2014-11-25 $33,083,000