Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12243806 | Nested architectures for enhanced heterogeneous integration | Ravindranath V. Mahajan, Debendra Mallik, Sujit Sharan | 2025-03-04 |
| 12183649 | IC package including multi-chip unit with bonded integrated heat spreader | Debendra Mallik, Ravindranath V. Mahajan | 2024-12-31 |
| 12176268 | Open cavity bridge co-planar placement architectures and processes | Omkar G. Karhade, Sairam Agraharam, Nitin A. Deshpande, Mitul Modi, Manish Dubey +1 more | 2024-12-24 |
| 12159813 | Embedded bridge die with through-silicon vias | Aditya S. Vaidya, Ravindranath V. Mahajan, Paul R. Start | 2024-12-03 |
| 12142545 | Nested architectures for enhanced heterogeneous integration | Ravindranath V. Mahajan, Debendra Mallik, Sujit Sharan | 2024-11-12 |
| 12068222 | Dummy die structures of a packaged integrated circuit device | Mitul Modi, Joseph Van Nausdle, Omkar G. Karhade, Edvin Cetegen, Nicholas S. Haehn +4 more | 2024-08-20 |
| 12027448 | Open cavity bridge power delivery architectures and processes | Omkar G. Karhade, Mitul Modi, Sairam Agraharam, Nitin A. Deshpande | 2024-07-02 |
| 12009318 | Control of warpage using ABF GC cavity for embedded die package | Ian En Yoon Chin, Daniel N. Sobieski | 2024-06-11 |
| 11978948 | Die with embedded communication cavity | Vijay K. Nair | 2024-05-07 |
| 11798865 | Nested architectures for enhanced heterogeneous integration | Ravindranath V. Mahajan, Debendra Mallik, Sujit Sharan | 2023-10-24 |
| 11749577 | IC package including multi-chip unit with bonded integrated heat spreader | Debendra Mallik, Ravindranath V. Mahajan | 2023-09-05 |
| 11742261 | Nested architectures for enhanced heterogeneous integration | Ravindranath V. Mahajan, Debendra Mallik, Sujit Sharan | 2023-08-29 |
| 11742270 | Landing pad apparatus for through-silicon-vias | — | 2023-08-29 |
| 11594493 | Ceramic interposers for on-die interconnects | — | 2023-02-28 |
| 11587851 | Embedded bridge with through-silicon vias | Aditya S. Vaidya, Ravindranath V. Mahajan, Paul R. Start | 2023-02-21 |
| 11581235 | IC package including multi-chip unit with bonded integrated heat spreader | Debendra Mallik, Ravindranath V. Mahajan | 2023-02-14 |
| 11569173 | Bridge hub tiling architecture | Andrew Collins, Wilfred Gomes, Ravindranath V. Mahajan, Sujit Sharan | 2023-01-31 |
| 11527489 | Apparatus and system with package stiffening magnetic inductor core and methods of making the same | Michael J. Hill, Mathew J. Manusharow, Beomseok Choi | 2022-12-13 |
| 11488880 | Enclosure for an electronic component | Vijay K. Nair | 2022-11-01 |
| 11417630 | Semiconductor package having passive support wafer | Debendra Mallik, Ravindranath V. Mahajan, Mitul Modi | 2022-08-16 |
| 11322457 | Control of warpage using ABF GC cavity for embedded die package | Ian En Yoon Chin, Daniel N. Sobieski | 2022-05-03 |
| 11239186 | Die with embedded communication cavity | Vijay K. Nair | 2022-02-01 |
| 11195806 | High frequency waveguide structure | Vijay K. Nair | 2021-12-07 |
| 11189573 | Semiconductor package with electromagnetic interference shielding using metal layers and vias | Vijay K. Nair | 2021-11-30 |
| 11145583 | Method to achieve variable dielectric thickness in packages for better electrical performance | Yidnekachew S. Mekonnen | 2021-10-12 |