Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11128029 | Die with embedded communication cavity | Vijay K. Nair | 2021-09-21 |
| 11049798 | Embedded bridge with through-silicon Vias | Aditya S. Vaidya, Ravindranath V. Mahajan, Paul R. Start | 2021-06-29 |
| 11011448 | IC package including multi-chip unit with bonded integrated heat spreader | Debendra Mallik, Ravindranath V. Mahajan | 2021-05-18 |
| 10804117 | Method to enable interposer to interposer connection | Ravindranath V. Mahajan | 2020-10-13 |
| 10707169 | Ceramic interposers for on-die interconnects | — | 2020-07-07 |
| 10421432 | Tamper resistant lock assembly having physical unclonable functions | Victoria C. Moore, Ned M. Smith | 2019-09-24 |
| 10403578 | Electronic device package | Vipul V. Mehta | 2019-09-03 |
| 10373888 | Electronic package assembly with compact die placement | Eric J. Li, Vipul V. Mehta | 2019-08-06 |
| 10375832 | Method of forming an interference shield on a substrate | Kemal Aygun, Daniel N. Sobieski, Drew W. Delaney | 2019-08-06 |
| 10373893 | Embedded bridge with through-silicon vias | Aditya S. Vaidya, Ravindranath V. Mahajan, Paul R. Start | 2019-08-06 |
| 10199354 | Die sidewall interconnects for 3D chip assemblies | Mitul Modi | 2019-02-05 |
| 9721906 | Electronic package with corner supports | Manish Dubey, Rajendra C. Dias, Baris Bicen, Bharat P. Penmecha | 2017-08-01 |
| 9716084 | Multichip integration with through silicon via (TSV) die embedded in package | Yonggang Li, Rahul N. Manepalli, Javier Soto Gonzalez | 2017-07-25 |
| 9520350 | Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer | Weng Hong Teh, Emile Davies-Venn, Ebrahim Andideh, Daniel N. Sobieski | 2016-12-13 |
| 9397079 | Multichip integration with through silicon via (TSV) die embedded in package | Yonggang Li, Rahul N. Manepalli, Javier Soto Gonzalez | 2016-07-19 |
| 9232686 | Thin film based electromagnetic interference shielding with BBUL/coreless packages | Kemal Aygun, Daniel N. Sobieski, Drew W. Delaney | 2016-01-05 |
| 9041207 | Method to increase I/O density and reduce layer counts in BBUL packages | Sairam Agraharam | 2015-05-26 |
| 9000599 | Multichip integration with through silicon via (TSV) die embedded in package | Yonggang Li, Rahul N. Manepalli, Javier Soto Gonzalez | 2015-04-07 |
| 8957013 | Receptors useful for gas phase chemical sensing | Justyn W. Jaworski, Seung-Wuk Lee, Arunava Majumdar | 2015-02-17 |
| 8158522 | Method of forming a deep trench in a substrate | Khalid Mohiuddin Sirajuddin, Jon C. Farr, Sharma Pamarthy | 2012-04-17 |