Issued Patents All Time
Showing 25 most recent of 198 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12341129 | Substrateless double-sided embedded multi-die interconnect bridge | Biancun Xie, Jianyong Xie, Debendra Mallik, Robert L. Sankman | 2025-06-24 |
| 12243812 | Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages | Dae-Woo Kim | 2025-03-04 |
| 12243806 | Nested architectures for enhanced heterogeneous integration | Ravindranath V. Mahajan, Debendra Mallik, Digvijay A. Raorane | 2025-03-04 |
| 12218063 | EMIB architecture with dedicated metal layers for improving power delivery | Jianyong Xie, Huang-Ta Chen | 2025-02-04 |
| 12170253 | Metal-free frame design for silicon bridges for semiconductor packages | Dae-Woo Kim, Sairam Agraharam | 2024-12-17 |
| 12142553 | Guard ring design enabling in-line testing of silicon bridges for semiconductor packages | Arnab Sarkar, Dae-Woo Kim | 2024-11-12 |
| 12142545 | Nested architectures for enhanced heterogeneous integration | Ravindranath V. Mahajan, Debendra Mallik, Digvijay A. Raorane | 2024-11-12 |
| 12113026 | Multi-chip package and method of providing die-to-die interconnects in same | Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz +1 more | 2024-10-08 |
| 12074121 | Metal-free frame design for silicon bridges for semiconductor packages | Dae-Woo Kim, Sairam Agraharam | 2024-08-27 |
| 12057413 | Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and cost | Lijiang Wang, Jianyong Xie, Arghya Sain, Xiaohong Jiang, Kemal Aygun | 2024-08-06 |
| 12044888 | Silicon groove architectures and manufacturing processes for passive alignment in a photonics die | Omkar G. Karhade, Xiaoqian Li, Nitin A. Deshpande | 2024-07-23 |
| 12046568 | Capacitor die embedded in package substrate for providing capacitance to surface mounted die | Andrew Collins, Jianyong Xie | 2024-07-23 |
| 11876053 | Multi-chip package and method of providing die-to-die interconnects in same | Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz +1 more | 2024-01-16 |
| 11848259 | Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages | Dae-Woo Kim | 2023-12-19 |
| 11824008 | Multi-chip package and method of providing die-to-die interconnects in same | Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz +1 more | 2023-11-21 |
| 11798865 | Nested architectures for enhanced heterogeneous integration | Ravindranath V. Mahajan, Debendra Mallik, Digvijay A. Raorane | 2023-10-24 |
| 11784150 | Rounded metal trace corner for stress reduction | Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks | 2023-10-10 |
| 11742261 | Nested architectures for enhanced heterogeneous integration | Ravindranath V. Mahajan, Debendra Mallik, Digvijay A. Raorane | 2023-08-29 |
| 11728294 | Capacitor die embedded in package substrate for providing capacitance to surface mounted die | Andrew Collins, Jianyong Xie | 2023-08-15 |
| 11694952 | Horizontal pitch translation using embedded bridge dies | Kemal Aygun, Zhiguo Qian, Yidnekachew S. Mekonnen, Zhichao Zhang, Jianyong Xie | 2023-07-04 |
| 11676889 | Guard ring design enabling in-line testing of silicon bridges for semiconductor packages | Arnab Sarkar, Dae-Woo Kim | 2023-06-13 |
| 11626372 | Metal-free frame design for silicon bridges for semiconductor packages | Dae-Woo Kim, Sairam Agraharam | 2023-04-11 |
| 11621223 | Interconnect hub for dies | Andrew Collins, Jianyong Xie | 2023-04-04 |
| 11569173 | Bridge hub tiling architecture | Andrew Collins, Digvijay A. Raorane, Wilfred Gomes, Ravindranath V. Mahajan | 2023-01-31 |
| 11462521 | Multilevel die complex with integrated discrete passive components | Andrew Collins, Jianyong Xie | 2022-10-04 |