Issued Patents All Time
Showing 26–50 of 198 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11387187 | Embedded very high density (VHD) layer | Andrew Collins, Jianyong Xie, Henning Braunisch, Aleksandar Aleksov | 2022-07-12 |
| 11380643 | Rounded metal trace corner for stress reduction | Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks | 2022-07-05 |
| 11355427 | Device, method and system for providing recessed interconnect structures of a substrate | Howe Yin Loo, Tin Poay Chuah, Ananth Prabhakumar | 2022-06-07 |
| 11322445 | EMIB copper layer for signal and power routing | Yidnekachew S. Mekonnen, Dae-Woo Kim, Kemal Aygun | 2022-05-03 |
| 11276635 | Horizontal pitch translation using embedded bridge dies | Kemal Aygun, Zhiguo Qian, Yidnekachew S. Mekonnen, Zhichao Zhang, Jianyong Xie | 2022-03-15 |
| 11257743 | Guard ring design enabling in-line testing of silicon bridges for semiconductor packages | Arnab Sarkar, Dae-Woo Kim | 2022-02-22 |
| 11222837 | Low-inductance current paths for on-package power distributions and methods of assembling same | Andrew Collins, Jianyong Xie | 2022-01-11 |
| 11222847 | Enabling long interconnect bridges | Ravindranath V. Mahajan, Zhiguo Qian, Henning Braunisch, Kemal Aygun | 2022-01-11 |
| 11195805 | Capacitor die embedded in package substrate for providing capacitance to surface mounted die | Andrew Collins, Jianyong Xie | 2021-12-07 |
| 11114394 | Signal routing carrier | Lijiang Wang, Jianyong Xie, Robert L. Sankman | 2021-09-07 |
| 11031288 | Passive components in vias in a stacked integrated circuit package | Ravindranath V. Mahajan, Stefan Rusu, Donald S. Gardner | 2021-06-08 |
| 10978423 | Projecting contacts and method for making the same | Dae-Woo Kim, Ravindranath V. Mahajan | 2021-04-13 |
| 10923429 | Multi-chip package and method of providing die-to-die interconnects in same | Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz +1 more | 2021-02-16 |
| 10916514 | Metal-free frame design for silicon bridges for semiconductor packages | Dae-Woo Kim, Sairam Agraharam | 2021-02-09 |
| 10797014 | Rounded metal trace corner for stress reduction | Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks | 2020-10-06 |
| 10763216 | Multi-chip package and method of providing die-to-die interconnects in same | Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz +1 more | 2020-09-01 |
| 10651117 | Low-inductance current paths for on-package power distributions and methods of assembling same | Andrew Collins, Jianyong Xie | 2020-05-12 |
| 10510669 | Multi-chip package and method of providing die-to-die interconnects in same | Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz +1 more | 2019-12-17 |
| 10475736 | Via architecture for increased density interface | Aleksandar Aleksov, Arnab Sarkar, Arghya Sain, Kristof Darmawikarta, Henning Braunisch +3 more | 2019-11-12 |
| 10461047 | Metal-free frame design for silicon bridges for semiconductor packages | Dae-Woo Kim, Sairam Agraharam | 2019-10-29 |
| 10418312 | Guard ring design enabling in-line testing of silicon bridges for semiconductor packages | Arnab Sarkar, Dae-Woo Kim | 2019-09-17 |
| 10236209 | Passive components in vias in a stacked integrated circuit package | Ravindranath V. Mahajan, Stefan Rusu, Donald S. Gardner | 2019-03-19 |
| 10177083 | Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages | Dae-Woo Kim | 2019-01-08 |
| 10002824 | Magnetic alignment for flip chip microelectronic devices | Ankur Agrawal, Srinivas S. Moola, Vijay Govindarajan | 2018-06-19 |
| 9875969 | Multi-chip package and method of providing die-to-die interconnects in same | Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Stefanie M. Lotz, Johanna M. Swan | 2018-01-23 |