JX

Jianyong Xie

IN Intel: 28 patents #1,356 of 30,777Top 5%
GR Georgia Tech Research: 1 patents #1,150 of 2,755Top 45%
Overall (All Time): #126,782 of 4,157,543Top 4%
29
Patents All Time

Issued Patents All Time

Showing 25 most recent of 29 patents

Patent #TitleCo-InventorsDate
12341129 Substrateless double-sided embedded multi-die interconnect bridge Biancun Xie, Sujit Sharan, Debendra Mallik, Robert L. Sankman 2025-06-24
12218063 EMIB architecture with dedicated metal layers for improving power delivery Sujit Sharan, Huang-Ta Chen 2025-02-04
12205924 Semiconductor packages with chiplets coupled to a memory device Andrew Collins 2025-01-21
12062616 Power delivery for embedded bridge die utilizing trench structures Kemal Aygun, Zhiguo Qian 2024-08-13
12057413 Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and cost Lijiang Wang, Arghya Sain, Xiaohong Jiang, Sujit Sharan, Kemal Aygun 2024-08-06
12046568 Capacitor die embedded in package substrate for providing capacitance to surface mounted die Andrew Collins, Sujit Sharan 2024-07-23
11887932 Dielectric-filled trench isolation of vias Kemal Aygun, Zhiguo Qian 2024-01-30
11837549 Power delivery for embedded bridge die utilizing trench structures Kemal Aygun, Zhiguo Qian 2023-12-05
11817391 Power delivery for embedded bridge die utilizing trench structures Kemal Aygun, Zhiguo Qian 2023-11-14
11728294 Capacitor die embedded in package substrate for providing capacitance to surface mounted die Andrew Collins, Sujit Sharan 2023-08-15
11694952 Horizontal pitch translation using embedded bridge dies Sujit Sharan, Kemal Aygun, Zhiguo Qian, Yidnekachew S. Mekonnen, Zhichao Zhang 2023-07-04
11621227 Power delivery for embedded bridge die utilizing trench structures Kemal Aygun, Zhiguo Qian 2023-04-04
11621223 Interconnect hub for dies Andrew Collins, Sujit Sharan 2023-04-04
11610862 Semiconductor packages with chiplets coupled to a memory device Andrew Collins 2023-03-21
11545416 Minimization of insertion loss variation in through-silicon vias (TSVs) Yidnekachew S. Mekonnen, Zhiguo Qian, Kemal Aygun 2023-01-03
11462521 Multilevel die complex with integrated discrete passive components Andrew Collins, Sujit Sharan 2022-10-04
11456281 Architecture and processes to enable high capacity memory packages through memory die stacking Yi Li, Zhiguo Qian, Prasad Ramanathan, Saikumar Jayaraman, Kemal Aygun +3 more 2022-09-27
11387187 Embedded very high density (VHD) layer Andrew Collins, Sujit Sharan, Henning Braunisch, Aleksandar Aleksov 2022-07-12
11296031 Dielectric-filled trench isolation of vias Kemal Aygun, Zhiguo Qian 2022-04-05
11276635 Horizontal pitch translation using embedded bridge dies Sujit Sharan, Kemal Aygun, Zhiguo Qian, Yidnekachew S. Mekonnen, Zhichao Zhang 2022-03-15
11222837 Low-inductance current paths for on-package power distributions and methods of assembling same Andrew Collins, Sujit Sharan 2022-01-11
11222848 Power delivery for embedded bridge die utilizing trench structures Kemal Aygun, Zhiguo Qian 2022-01-11
11195805 Capacitor die embedded in package substrate for providing capacitance to surface mounted die Andrew Collins, Sujit Sharan 2021-12-07
11114394 Signal routing carrier Lijiang Wang, Sujit Sharan, Robert L. Sankman 2021-09-07
10950550 Semiconductor package with through bridge die connections Zhiguo Qian, Kemal Aygun 2021-03-16