Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor package having wafer-level active die and external die mount

Semiconductor package having wafer-level active die and external die mount

US Patent 11545441 · Granted Jan 3, 2023

Estimated economic value: $15,575,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Package architecture of photonic system with vertically stacked dies having plan2025
Package architecture of scalable compute wall having compute bricks with vertica2025
Ultra-thin, hyper-density semiconductor packages2025
Ultra-thin, hyper-density semiconductor packages2025
Ultra-thin, hyper-density semiconductor packages2025
Multi-chip packaging2025
Moisture seal coating of hybrid bonded stacked die package assembly2025
Nested glass packaging architecture for hybrid electrical and optical communicat2025
Microelectronic structures including bridges2025
Edge-aligned template structure for integrated circuit packages2025
Ultra-thin, hyper-density semiconductor packages2025
Ultra-thin, hyper-density semiconductor packages2025