Issued Patents All Time
Showing 126–150 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7467325 | Processor instruction retry recovery | Susan E. Eisen, Michael J. Mack, Dung Q. Nguyen, Jose Angel Paredes, Scott Barnett Swaney | 2008-12-16 |
| 7444498 | Load lookahead prefetch for microprocessors | Richard J. Eickemeyer, Dung Q. Nguyen, Benjamin W. Stolt, Brian W. Thompto | 2008-10-28 |
| 7421567 | Using a modified value GPR to enhance lookahead prefetch | Richard J. Eickemeyer, Dung Q. Nguyen, Benjamin W. Stolt, Brian W. Thompto | 2008-09-02 |
| 7395414 | Dynamic recalculation of resource vector at issue queue for steering of dependent instructions | Dung Q. Nguyen, Brian W. Thompto, Raymond Cheung Yeung | 2008-07-01 |
| 7392366 | Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches | Pradip Bose, Alper Buyuktosunoglu, Richard J. Eickemeyer, Lee Evan Eisen, Philip G. Emma +4 more | 2008-06-24 |
| 7380066 | Store stream prefetching in a microprocessor | John B. Griswell, Jr., Francis Patrick O'Connell, William J. Starke, Jeffrey A. Stuecheli, Albert Thomas Williams | 2008-05-27 |
| 7350029 | Data stream prefetching in a microprocessor | Eric Jason Fluhr, Bradly G. Frey, John B. Griswell, Jr., Cathy May, Francis Patrick O'Connell +2 more | 2008-03-25 |
| 7302553 | Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue | Sam Gat-Shang Chu, Dung Q. Nguyen | 2007-11-27 |
| 7278011 | Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table | Susan E. Eisen, David Arnold Luick, Dung Q. Nguyen | 2007-10-02 |
| 7269715 | Instruction grouping history on fetch-side dispatch group formation | David S. Levitan, John W. Ward, III | 2007-09-11 |
| 7254697 | Method and apparatus for dynamic modification of microprocessor instruction group at dispatch | James Wilson Bishop, Jafar Nahidi, Dung Q. Nguyen, Brian W. Thompto | 2007-08-07 |
| 7237094 | Instruction group formation and mechanism for SMT dispatch | Brian W. Curran, Brian R. Konigsburg, David Arnold Luick, Dung Q. Nguyen | 2007-06-26 |
| 7194603 | SMT flush arbitration | William E. Burky, Dung Q. Nguyen, David A. Schroter | 2007-03-20 |
| 7080241 | Mechanism for self-initiated instruction issuing and method therefor | Hoichi Cheong | 2006-07-18 |
| 7051177 | Method for measuring memory latency in a hierarchical memory system | Alexander Erik Mericas, Robert Dominick Mirabella, Toshihiko Kurihara, Michitaka Okuno, Masahiro Tokoro | 2006-05-23 |
| 7047398 | Analyzing instruction completion delays in a processor | Toshihiko Kurihara, Alexander Erik Mericas, Robert Dominick Mirabella, Michitaka Okuno, Masahiro Tokoro | 2006-05-16 |
| 6988186 | Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry | Richard J. Eickemeyer, Steven R. Kunkel | 2006-01-17 |
| 6970999 | Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters | Toshihiko Kurihara, Alexander Erik Mericas, Robert Dominick Mirabella, Hideki Mitsubayashi, Michitaka Okuno +1 more | 2005-11-29 |
| 6910120 | Speculative counting of performance events with rewind counter | Alexander Erik Mericas, Robert Dominick Mirabella, Toshihiko Kurihara, Michitaka Okuno, Masahiro Tokoro | 2005-06-21 |
| 6898696 | Method and system for efficiently restoring a processor's execution state following an interrupt caused by an interruptible instruction | Hoichi Cheong | 2005-05-24 |
| 6826678 | Completion monitoring in a processor having multiple execution units with various latencies | Dung Q. Nguyen | 2004-11-30 |
| 6721874 | Method and system for dynamically shared completion table supporting multiple threads in a processing system | Peichun Peter Liu, Balaram Sinharoy | 2004-04-13 |
| 6658534 | Mechanism to reduce instruction cache miss penalties and methods therefor | Steven Wayne White, Kurt A. Feiste, Paul J. Jordan | 2003-12-02 |
| 6658555 | Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline | James Allan Kahle, Charles Roberts Moore, David Shippy, Larry Edward Thatcher | 2003-12-02 |
| 6654876 | System for rejecting and reissuing instructions after a variable delay time period | David Shippy | 2003-11-25 |