Issued Patents All Time
Showing 176–195 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5996085 | Concurrent execution of machine context synchronization operations and non-interruptible instructions | Hoichi Cheong | 1999-11-30 |
| 5983341 | Data processing system and method for extending the time for execution of an instruction | Hoichi Cheong, Paul J. Jordan | 1999-11-09 |
| 5974524 | Method and apparatus for reducing the number of rename registers in a processor supporting out-of-order execution | Hoichi Cheong, Paul J. Jordan, Quan Nguyen | 1999-10-26 |
| 5963723 | System for pairing dependent instructions having non-contiguous addresses during dispatch | — | 1999-10-05 |
| 5913048 | Dispatching instructions in a processor supporting out-of-order execution | Hoichi Cheong, John Stephen Muhich, Steven Wayne White | 1999-06-15 |
| 5887161 | Issuing instructions in a processor supporting out-of-order execution | Hoichi Cheong, John Stephen Muhich, Steven Wayne White | 1999-03-23 |
| 5875326 | Data processing system and method for completing out-of-order instructions | Hoichi Cheong, Paul J. Jordan | 1999-02-23 |
| 5870612 | Method and apparatus for condensed history buffer | Hoichi Cheong, John Stephen Muhich, Steven Wayne White | 1999-02-09 |
| 5870582 | Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched | Hoichi Cheong, John Stephen Muhich, Steven Wayne White | 1999-02-09 |
| 5864341 | Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding | Troy N. Hicks, John Stephen Muhich, Steven Wayne White | 1999-01-26 |
| 5860014 | Method and apparatus for improved recovery of processor state using history buffer | Hoichi Cheong, John Stephen Muhich, Steven Wayne White | 1999-01-12 |
| 5841999 | Information handling system having a register remap structure using a content addressable table | Erdem Hokenek | 1998-11-24 |
| 5822752 | Method and apparatus for fast parallel determination of queue entries | Hoichi Cheong, Michael Kevin Ciraula, John Stephen Muhich | 1998-10-13 |
| 5805849 | Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions | Paul J. Jordan, Brian R. Konigsburg, Steven Wayne White | 1998-09-08 |
| 5805906 | Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions | Hoichi Cheong, Paul J. Jordan | 1998-09-08 |
| 5805876 | Method and system for reducing average branch resolution time and effective misprediction penalty in a processor | Pradip Bose, Kin Shing Chan, Robert Eric Wasmuth | 1998-09-08 |
| 5774712 | Instruction dispatch unit and method for mapping a sending order of operations to a receiving order | Hoichi Cheong | 1998-06-30 |
| 5754885 | Apparatus and method for selecting entries from an array | Hoichi Cheong, Tom Tien-Cheng Chiu, Donald George Mikan, Jr. | 1998-05-19 |
| 5699538 | Efficient firm consistency support mechanisms in an out-of-order execution superscaler multiprocessor | Kimming So, Bao-Binh Truong | 1997-12-16 |
| 5465336 | Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system | Benjamin Imai, Dung Q. Nguyen | 1995-11-07 |