Issued Patents All Time
Showing 151–175 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6654869 | Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling | James Allan Kahle, Charles Roberts Moore | 2003-11-25 |
| 6631463 | Method and apparatus for patching problematic instructions in a microprocessor using software interrupts | Michael Stephen Floyd, James Allan Kahle, John Anthony Moore, Kevin F. Reick, Edward John Silha | 2003-10-07 |
| 6553480 | System and method for managing the execution of instruction groups having multiple executable instructions | Hoichi Cheong | 2003-04-22 |
| 6543002 | Recovery from hang condition in a microprocessor | James Allan Kahle, Kevin F. Reick, David Shippy, Larry Edward Thatcher | 2003-04-01 |
| 6543003 | Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor | Michael Stephen Floyd, James Allan Kahle, Larry Scott Leitner, Kevin F. Reick | 2003-04-01 |
| 6535973 | Method and system for speculatively issuing instructions | Hoichi Cheong, Maureen A. Delaney, Robert G. McDonald, Dung Q. Nguyen, David Wayne Victor | 2003-03-18 |
| 6480931 | Content addressable storage apparatus and register mapper architecture | Taqi Nasser Buti, Peter Juergen Klim, Robert G. McDonald | 2002-11-12 |
| 6473850 | System and method for handling instructions occurring after an ISYNC instruction | Hoichi Cheong, R. Hay, James Allan Kahle | 2002-10-29 |
| 6463524 | Superscalar processor and method for incrementally issuing store instructions | Maureen A. Delaney, Dung Q. Nguyen, Robert G. McDonald, David Wayne Victor | 2002-10-08 |
| 6442675 | Compressed string and multiple generation engine | John Edward Derrick, Lee Evan Eisen | 2002-08-27 |
| 6430678 | Scoreboard mechanism for serialized string operations utilizing the XER | James Allan Kahle, Lee Evan Eisen, John Edward Derrick, Robert William Hay | 2002-08-06 |
| 6356918 | Method and system for managing registers in a data processing system supports out-of-order and speculative instruction execution | Chiao-Mei Chuang | 2002-03-12 |
| 6345356 | Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs | John Edward Derrick, Lee Evan Eisen, Robert G. McDonald | 2002-02-05 |
| 6336183 | System and method for executing store instructions | Robert G. McDonald, David Shippy, Larry Edward Thatcher | 2002-01-01 |
| 6324640 | System and method for dispatching groups of instructions using pipelined register renaming | Hoichi Cheong | 2001-11-27 |
| 6311267 | Just-in-time register renaming technique | Dung Q. Nguyen | 2001-10-30 |
| 6308260 | Mechanism for self-initiated instruction issuing and method therefor | Hoichi Cheong | 2001-10-23 |
| 6298435 | Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor | Kin Shing Chan, Dung Q. Nguyen | 2001-10-02 |
| 6298436 | Method and system for performing atomic memory accesses in a processor system | James Allan Kahle, Larry Edward Thatcher, David Shippy | 2001-10-02 |
| 6289428 | Superscaler processor and method for efficiently recovering from misaligned data addresses | John Edward Derrick, David Shippy, Larry Edward Thatcher | 2001-09-11 |
| 6286094 | Method and system for optimizing the fetching of dispatch groups in a superscalar processor | John Edward Derrick, Lee Evan Eisen, Brian R. Konigsburg | 2001-09-04 |
| 6237081 | Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor | Larry Edward Thatcher, Bruce Joseph Ronchetti, David Shippy | 2001-05-22 |
| 6098167 | Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution | Hoichi Cheong, John Stephen Muhich, Steven Wayne White | 2000-08-01 |
| 6070235 | Data processing system and method for capturing history buffer data | Hoichi Cheong | 2000-05-30 |
| 6061777 | Apparatus and method for reducing the number of rename registers required in the operation of a processor | Hoichi Cheong, Paul J. Jordan, Soummya Mallick | 2000-05-09 |