Issued Patents All Time
Showing 76–100 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9690586 | Processing of multiple instruction streams in a parallel slice processor | Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more | 2017-06-27 |
| 9672043 | Processing of multiple instruction streams in a parallel slice processor | Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more | 2017-06-06 |
| 9665372 | Parallel slice processor with dynamic instruction stream mapping | Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more | 2017-05-30 |
| 9626187 | Transactional memory system supporting unbroken suspended execution | Harold W. Cain, III, Bradly G. Frey, Benjamin Herrenschmidt, Cathy May, Maged M. Michael +4 more | 2017-04-18 |
| 9626256 | Determining failure context in hardware transactional memories | Harold W. Cain, III, Bradly G. Frey, Cathy May | 2017-04-18 |
| 9619345 | Apparatus for determining failure context in hardware transactional memories | Harold W. Cain, III, Bradly G. Frey, Cathy May | 2017-04-11 |
| 9524171 | Split-level history buffer in a computer processing unit | Dung Q. Nguyen, David R. Terry | 2016-12-20 |
| 9519479 | Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction | Jose E. Moreira, Pratap C. Pattnaik, Brian W. Thompto, Jessica Hui-Chun Tseng | 2016-12-13 |
| 9268598 | Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories | Robert J. Blainey, Harold W. Cain, III, Susan E. Eisen, Bradly G. Frey, Charles B. Hall +1 more | 2016-02-23 |
| 9268599 | Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories | Robert J. Blainey, Harold W. Cain, III, Susan E. Eisen, Bradley G. Frey, Charles B. Hall +1 more | 2016-02-23 |
| 9086987 | Detection of conflicts between transactions and page shootdowns | Harold W. Cain, III, Bryan Lloyd, Shih-Hsiung S. Tung | 2015-07-21 |
| 9086986 | Detection of conflicts between transactions and page shootdowns | Harold W. Cain, III, Bryan Lloyd, Shih-Hsiung S. Tung | 2015-07-21 |
| 9081607 | Conditional transaction abort and precise abort handling | Robert J. Blainey, Harold W. Cain, III, Bradly G. Frey, Cathy May | 2015-07-14 |
| 9037837 | Hardware assist thread for increasing code parallelism | Ronald P. Hall, Raul E. Silvera, Balaram Sinharoy | 2015-05-19 |
| 8874880 | Instruction tracking system for processors | Christopher M. Abernathy, Dung Q. Nguyen, Benjamin W. Stolt | 2014-10-28 |
| 8725993 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James Allan Kahle, Dung Q. Nguyen | 2014-05-13 |
| 8683175 | Seamless interface for multi-threaded core accelerators | Kattamuri Ekanadham, Jose E. Moreira, Pratap C. Pattnaik | 2014-03-25 |
| 8661228 | Multi-level register file supporting multiple threads | Christopher M. Abernathy, Mary D. Brown, Dung Q. Nguyen | 2014-02-25 |
| 8661227 | Multi-level register file supporting multiple threads | Christopher M. Abernathy, Mary D. Brown, Dung Q. Nguyen | 2014-02-25 |
| 8631223 | Register file supporting transactional processing | Christopher M. Abernathy, Mary D. Brown, Dung Q. Nguyen | 2014-01-14 |
| 8521998 | Instruction tracking system for processors | Christopher M. Abernathy, Dung Q. Nguyen, Benjamin W. Stolt | 2013-08-27 |
| 8423750 | Hardware assist thread for increasing code parallelism | Ronald P. Hall, Raul E. Silvera, Balaram Sinharoy | 2013-04-16 |
| 8418180 | Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors | James Wilson Bishop, Dung Q. Nguyen, Balaram Sinharoy, Brian W. Thompto, Raymond Cheung Yeung | 2013-04-09 |
| 8347068 | Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor | Richard J. Eickemeyer, Dung Q. Nguyen, Balaram Sinharoy | 2013-01-01 |
| 8145887 | Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor | Dung Q. Nguyen | 2012-03-27 |