Issued Patents All Time
Showing 26–50 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10877763 | Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor | Bryan Lloyd, Brian D. Barrick, Kurt A. Feiste, Dung Q. Nguyen, Kenneth L. Ward | 2020-12-29 |
| 10831537 | Dynamic update of the number of architected registers assigned to software threads using spill counts | Harold W. Cain, III, Hubertus Franke, Charles Ray Johns, Ravi Nair | 2020-11-10 |
| 10831501 | Managing an issue queue for fused instructions and paired instructions in a microprocessor | Michael J. Genden, Dung Q. Nguyen, Brian W. Thompto | 2020-11-10 |
| 10831498 | Managing an issue queue for fused instructions and paired instructions in a microprocessor | Michael J. Genden, Dung Q. Nguyen, Brian W. Thompto | 2020-11-10 |
| 10831481 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Jentje Leenstra, Dung Q. Nguyen +2 more | 2020-11-10 |
| 10761856 | Instruction completion table containing entries that share instruction tags | Kenneth L. Ward, Dung Q. Nguyen, Susan E. Eisen | 2020-09-01 |
| 10747545 | Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor | Michael J. Genden, Dung Q. Nguyen, Brian W. Thompto | 2020-08-18 |
| 10691459 | Converting multiple instructions into a single combined instruction with an extension opcode | Giles R. Frazier, Jose E. Moreira, Brian W. Thompto | 2020-06-23 |
| 10684856 | Converting multiple instructions into a single combined instruction with an extension opcode | Giles R. Frazier, Jose E. Moreira, Brian W. Thompto | 2020-06-16 |
| 10664275 | Speeding up younger store instruction execution after a sync instruction | Susan E. Eisen, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt +1 more | 2020-05-26 |
| 10635444 | Shared compare lanes for dependency wake up in a pair-based issue queue | Michael J. Genden, Dung Q. Nguyen, Brian W. Thomto | 2020-04-28 |
| 10564978 | Operation of a multi-slice processor with an expanded merge fetching queue | Kimberly M. Fernsler, David A. Hrusecky, Elizabeth A. McGlone, Brian W. Thompto | 2020-02-18 |
| 10545765 | Multi-level history buffer for transaction memory in a microprocessor | Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Dung Q. Nguyen, David R. Terry +1 more | 2020-01-28 |
| 10545762 | Independent mapping of threads | Sam Gat-Shang Chu, Markus Kaltenbach, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen +1 more | 2020-01-28 |
| 10496406 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Jentje Leenstra, Dung Q. Nguyen +2 more | 2019-12-03 |
| 10409598 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Jentje Leenstra, Dung Q. Nguyen +2 more | 2019-09-10 |
| 10394565 | Managing an issue queue for fused instructions and paired instructions in a microprocessor | Michael J. Genden, Dung Q. Nguyen, Brian W. Thompto | 2019-08-27 |
| 10387147 | Managing an issue queue for fused instructions and paired instructions in a microprocessor | Michael J. Genden, Dung Q. Nguyen, Brian W. Thompto | 2019-08-20 |
| 10296339 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James Allan Kahle, Dung Q. Nguyen | 2019-05-21 |
| 10289415 | Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data | Susan E. Eisen, Cliff Kucharski, Dung Q. Nguyen, David R. Terry | 2019-05-14 |
| 10282205 | Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions | Susan E. Eisen, Cliff Kucharski, Dung Q. Nguyen, David R. Terry | 2019-05-07 |
| 10268518 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Elizabeth A. McGlone | 2019-04-23 |
| 10255107 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Elizabeth A. McGlone | 2019-04-09 |
| 10241800 | Split-level history buffer in a computer processing unit | Dung Q. Nguyen, David R. Terry | 2019-03-26 |
| 10223125 | Linkable issue queue parallel execution slice processing method | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen, Brian W. Thompto | 2019-03-05 |