Issued Patents All Time
Showing 26–50 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7220642 | Protection of active layers of memory cells during processing of other elements | Steven C. Avanzino, Igor Sokolik, Suzette K. Pangrle, Nicholas H. Tripsas | 2007-05-22 |
| 7199416 | Systems and methods for a memory and/or selection element formed within a recess in a metal line | Nicholas H. Tripsas, Minh Quoc Tran | 2007-04-03 |
| 7135396 | Method of making a semiconductor structure | Calvin T. Gabriel | 2006-11-14 |
| 7091088 | UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing | Ning Cheng, Clarence B. Ferguson, Emmanuil H. Lingunis, Minh Van Ngo, Joerg Reiss +2 more | 2006-08-15 |
| 7071101 | Sacrificial TiN arc layer for increased pad etch throughput | Kelwin Ko | 2006-07-04 |
| 7018896 | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing | Minh Van Ngo, Tazrien Kamal, Mark T. Ramsbey, Arvind Halliyal, Jaeyong Park +6 more | 2006-03-28 |
| 7012008 | Dual spacer process for non-volatile memory devices | Tuan Pham, Mark T. Ramsbey, Yu Sun, Angela T. Hui, Maria C. Chan | 2006-03-14 |
| 6969654 | Flash NVROM devices with UV charge immunity | Tuan Pham, Mark T. Ramsbey, Angela T. Hui, Dawn Hopper | 2005-11-29 |
| 6794298 | CF4+H2O plasma ashing for reduction of contact/via resistance | Lu You, Mohammad R. Rakhshandehroo | 2004-09-21 |
| 6774432 | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL | Minh Van Ngo, Tazrien Kamal, Mark T. Ramsbey, Arvind Halliyal, Jaeyong Park +6 more | 2004-08-10 |
| 6709924 | Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate | Allen S. Yu, Allison Holbrook | 2004-03-23 |
| 6667243 | Etch damage repair with thermal annealing | Mark T. Ramsbey, Nicholas H. Tripsas, Arvind Halliyal, Yider Wu | 2003-12-23 |
| 6653231 | Process for reducing the critical dimensions of integrated circuit device features | Uzodinma Okoroanyanwu, Chih-Yuh Yang | 2003-11-25 |
| 6630288 | Process for forming sub-lithographic photoresist features by modification of the photoresist surface | Uzodinma Okoroanyanwu, Chih-Yuh Yang | 2003-10-07 |
| 6620717 | Memory with disposable ARC for wordline formation | Tazrien Kamal, Scott A. Bell, Kouros Ghandehari, Mark T. Ramsbey, Jean Y. Yang | 2003-09-16 |
| 6617215 | Memory wordline hard mask | Arvind Halliyal, Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey, Jean Y. Yang +3 more | 2003-09-09 |
| 6589709 | Process for preventing deformation of patterned photoresist features | Uzodinma Okoroanyanwu, Chih-Yuh Yang | 2003-07-08 |
| 6562723 | Hybrid stack method for patterning source/drain areas | Bharath Rangarajan, Ursula Q. Quinto | 2003-05-13 |
| 6551923 | Dual width contact for charge gain reduction | Bharath Rangarajan | 2003-04-22 |
| 6537866 | Method of forming narrow insulating spacers for use in reducing minimum component size | Tuan Pham, Jusuke Ogura, Bharath Rangarajan, Simon S. Chan | 2003-03-25 |
| 6522013 | Punch-through via with conformal barrier liner | Robert Chen, Robert Dawson, Khanh Tran | 2003-02-18 |
| 6500768 | Method for selective removal of ONO layer | Jiahua Huang, Jean Y. Yang | 2002-12-31 |
| 6500757 | Method and apparatus for controlling grain growth roughening in conductive stacks | Guarionex Morales | 2002-12-31 |
| 6492257 | Water vapor plasma for effective low-k dielectric resist stripping | Lu You, Mohammad R. Rakhshandehroo | 2002-12-10 |
| 6486506 | Flash memory with less susceptibility to charge gain and charge loss | Stephen Keetai Park | 2002-11-26 |