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Jeffrey A. Shields

AM AMD: 65 patents #74 of 9,279Top 1%
SL Spansion Llc.: 14 patents #50 of 769Top 7%
AT Adesto Technologies: 10 patents #14 of 52Top 30%
MI Microchip Technology Incorporated: 6 patents #97 of 958Top 15%
Fujitsu Limited: 3 patents #8,614 of 24,456Top 40%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
📍 Chandler, AZ: #23 of 3,331 inventorsTop 1%
🗺 Arizona: #157 of 32,909 inventorsTop 1%
Overall (All Time): #18,428 of 4,157,543Top 1%
89
Patents All Time

Issued Patents All Time

Showing 76–89 of 89 patents

Patent #TitleCo-InventorsDate
6130169 Efficient in-situ resist strip process for heavy polymer metal etch King Wai Kelwin Ko, Leobardo Mercado 2000-10-10
6127259 Phosphoric acid process for removal of contact BARC layer Bharath Rangarajan 2000-10-03
6114766 Integrated circuit with metal features presenting a larger landing area for vias 2000-09-05
6087724 HSQ with high plasma etching resistance surface for borderless vias Khanh Tran, Robert Chen, Robert Dawson 2000-07-11
6083850 HSQ dielectric interlayer 2000-07-04
6083851 HSQ with high plasma etching resistance surface for borderless vias Khanh Tran, Robert Chen, Robert Dawson 2000-07-04
6084290 HSQ dielectric interlayer 2000-07-04
6066546 Method to minimize particulate induced clamping failures Anne E. Sanderfer 2000-05-23
6060384 Borderless vias with HSQ gap filled patterned metal layers Robert Chen, Robert Dawson, Khanh Tran 2000-05-09
6043147 Method of prevention of degradation of low dielectric constant gap-fill material Robert Chen, Robert Dawson, Khanh Tran 2000-03-28
6010965 Method of forming high integrity vias 2000-01-04
5973387 Tapered isolated metal profile to reduce dielectric layer cracking Robert Chen, Khanh Tran 1999-10-26
5958798 Borderless vias without degradation of HSQ gap fill layers 1999-09-28
5866945 Borderless vias with HSQ gap filled patterned metal layers Robert Chen, Robert Dawson, Khanh Tran 1999-02-02