Issued Patents All Time
Showing 51–75 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6479348 | Method of making memory wordline hard mask extension | Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey, Jean Y. Yang, Emmanuil Lingunis +2 more | 2002-11-12 |
| 6472751 | H2 diffusion barrier formation by nitrogen incorporation in oxide layer | Robert Chen, Robert Dawson, Khanh Tran | 2002-10-29 |
| 6440874 | High throughput plasma resist strip process for temperature sensitive applications | — | 2002-08-27 |
| 6441418 | Spacer narrowed, dual width contact for charge gain reduction | Bharath Rangarajan | 2002-08-27 |
| 6426301 | Reduction of via etch charging damage through the use of a conducting hard mask | Ramkumar Subramanian, Bharath Rangarajan, Allen S. Yu | 2002-07-30 |
| 6412498 | Low temperature plasma strip process | — | 2002-07-02 |
| 6383945 | High selectivity pad etch for thick topside stacks | Jiahua Huang, Allison Holbrook | 2002-05-07 |
| 6376877 | Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor | Allen S. Yu | 2002-04-23 |
| 6350696 | Spacer etch method for semiconductor device | Jeffrey P. Erhardt | 2002-02-26 |
| 6316345 | High-temperature fluorinated chemistry removal of contact BARC layer | — | 2001-11-13 |
| 6274475 | Specialized metal profile for via landing areas | — | 2001-08-14 |
| 6265273 | Method of forming rectangular shaped spacers | Steven C. Avanzino, Stephen Keetai Park, Bharath Rangarajan, Larry Wang, Guarionex Morales | 2001-07-24 |
| 6261956 | Modified product mask for bridging detection | — | 2001-07-17 |
| 6245681 | Dual temperature nitride strip process | — | 2001-06-12 |
| 6239006 | Native oxide removal with fluorinated chemistry before cobalt silicide formation | — | 2001-05-29 |
| 6236595 | Programming method for a memory cell | Donald S. Gerber, Kent Hewitt, David Marc Davies | 2001-05-22 |
| 6232635 | Method to fabricate a high coupling flash cell with less silicide seam problem | Larry Wang, Steven C. Avanzino, Stephen Keetai Park | 2001-05-15 |
| 6222761 | Method for minimizing program disturb in a memory cell | Donald S. Gerber, Kent Hewitt | 2001-04-24 |
| 6214742 | Post-via tin removal for via resistance improvement | Allen S. Yu | 2001-04-10 |
| 6207582 | Native oxide removal with fluorinated chemistry before cobalt silicide formation using nitride spacers | Bharath Rangarajan | 2001-03-27 |
| 6194328 | H2 diffusion barrier formation by nitrogen incorporation in oxide layer | Robert Chen, Robert Dawson, Khanh Tran | 2001-02-27 |
| 6180534 | Borderless vias without degradation of HSQ gap fill layers | — | 2001-01-30 |
| 6177355 | Pad etch process capable of thick titanium nitride arc removal | Mark Russell Anderson | 2001-01-23 |
| 6174819 | Low temperature photoresist removal for rework during metal mask formation | Lewis Shen, Anne E. Sanderfer | 2001-01-16 |
| 6153504 | Method of using a silicon oxynitride ARC for final metal layer | Bharath Rangarajan | 2000-11-28 |