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Shared source line memory architecture for flash cell byte-alterable high endurance data memory |
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2021-02-02 |
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EEPROM memory cell with low voltage read path and high voltage erase/write path |
Jack T. Wong, Bomy Chen, Sonu Daryanani, Jeffrey A. Shields, Daniel A. Alvarez +1 more |
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Resistive random access memory (ReRAM) and conductive bridging random access memory (CBRAM) cross coupled fuse and read method and system |
Traian Bontas, Claudiu-Dumitru Nechifor, Iulian Dumitru |
2016-05-17 |
| 8094503 |
Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits |
Jeffrey A. Shields, Donald S. Gerber |
2012-01-10 |
| 7817474 |
Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits |
Jeffrey A. Shields, Donald S. Gerber |
2010-10-19 |
| 7466591 |
Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits |
Jeffrey A. Shields, Donald S. Gerber |
2008-12-16 |
| 6504191 |
Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor |
Donald S. Gerber, Randy Yach, Gianpaolo Spadini |
2003-01-07 |
| 6300183 |
Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor |
Donald S. Gerber, Randy Yach, Gianpaolo Spadini |
2001-10-09 |
| 6236595 |
Programming method for a memory cell |
Donald S. Gerber, Jeffrey A. Shields, David Marc Davies |
2001-05-22 |
| 6222761 |
Method for minimizing program disturb in a memory cell |
Donald S. Gerber, Jeffrey A. Shields |
2001-04-24 |
| 6150864 |
Time delay circuit which is voltage independent |
Randy Yach, David M. Susak |
2000-11-21 |
| 5764099 |
Integrated voltage regulating circuit useful in high voltage electronic encoders |
— |
1998-06-09 |
| 5675534 |
Method and apparatus for preventing unauthorized access to nonvolatile memory in electronic encoders having a voltage level detection circuit |
Willem Smit |
1997-10-07 |
| 5675622 |
Method and apparatus for electronic encoding and decoding |
Willem Smit, Emile VAN ROOYEN, Frederick Johannes Bruwer |
1997-10-07 |
| 5604701 |
Initializing a read pipeline of a non-volatile sequential memory device |
Samuel E. Alexander |
1997-02-18 |
| 5488711 |
Serial EEPROM device and associated method for reducing data load time using a page mode write cache |
Samuel E. Alexander, Richard J. Fisher |
1996-01-30 |
| 5367484 |
Programmable high endurance block for EEPROM device |
Samuel E. Alexander, Stephen V. Drehobl, Richard J. Fisher, Leonard F. French |
1994-11-22 |
| 5363334 |
Write protection security for memory device |
Samuel E. Alexander, Richard J. Fisher |
1994-11-08 |