Issued Patents 2017
Showing 76–100 of 109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9633869 | Packages with interposers and methods for forming the same | Sao-Ling Chiu, Kuo-Ching Hsu, Wei-Cheng Wu, Ping-Kang Huang, Shang-Yun Hou +1 more | 2017-04-25 |
| 9633963 | Packaging devices and methods of manufacture thereof | Hsien-Wei Chen, Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii | 2017-04-25 |
| 9633924 | Package structure and method for forming the same | Jing-Cheng Lin, Tsei-Chung Fu | 2017-04-25 |
| 9633917 | Three dimensional integrated circuit structure and method of manufacturing the same | Wen-Ching Tsai, Ming-Fa Chen | 2017-04-25 |
| 9633900 | Method for through silicon via structure | Shin-Puu Jeng, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai | 2017-04-25 |
| 9633870 | System and method for an improved interconnect structure | Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Tsung-Yuan Yu | 2017-04-25 |
| 9627365 | Tri-layer CoWoS structure | Shang-Yun Hou, Yun-Han Lee | 2017-04-18 |
| 9620488 | Three-dimensional integrated circuit structure and bonded structure | Sung-Feng Yeh, Ming-Fa Chen | 2017-04-11 |
| 9618572 | Testing of semiconductor chips with microbumps | Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng, Chao-Hsiang Yang | 2017-04-11 |
| 9613926 | Wafer to wafer bonding process and structures | Ming-Fa Chen, Wen-Ching Tsai | 2017-04-04 |
| 9613914 | Post-passivation interconnect structure | Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii | 2017-04-04 |
| 9601353 | Packages with molding structures and methods of forming the same | Chih-Fan Huang, Cheng-Tar Wu, Ming-Da Cheng, Chung-Shi Liu | 2017-03-21 |
| 9601463 | Fan-out stacked system in package (SIP) and the methods of making the same | Kuo-Chung Yee | 2017-03-21 |
| 9589857 | Interposer test structures and methods | Tzuan-Horng Liu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou +1 more | 2017-03-07 |
| 9589941 | Multi-chip package system and methods of forming the same | Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu | 2017-03-07 |
| 9589932 | Interconnect structures for wafer level package and methods of forming same | Chung-Shi Liu | 2017-03-07 |
| 9588505 | Near non-adaptive virtual metrology and chamber control | Tzu-Yu Wang, Chien Rhone Wang, Henry Lo, Jung Cheng Ko, Chih-Wei Lai +1 more | 2017-03-07 |
| 9583415 | Packages with thermal interface material on the sidewalls of stacked dies | Wensen Hung, Szu-Po Huang, An-Jhih Su, Hsiang-Fan Lee, Kim Hong Chen +2 more | 2017-02-28 |
| 9583365 | Method of forming interconnects for three dimensional integrated circuit | Chun-Hui Yu, Kuo-Chung Yee, Yeong-Jyh Lin, Chia-Hsiang Lin, Liang-Ju Yen +1 more | 2017-02-28 |
| 9576926 | Pad structure design in fan-out package | Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen | 2017-02-21 |
| 9576929 | Multi-strike process for bonding | Tung-Liang Shao, Chih-Hang Tung, Wen-Lin Shih, Hsiao-Yun Chen | 2017-02-21 |
| 9576910 | Semiconductor packaging structure and manufacturing method thereof | Ming-Da Cheng, Jui-Pin Hung | 2017-02-21 |
| 9570366 | Passivation layer for packaged chip | Shin-Puu Jeng, Wei-Cheng Wu, Shang-Yun Hou, Tzuan-Horng Liu, Tzu-Wei Chiu +1 more | 2017-02-14 |
| 9570324 | Method of manufacturing package system | Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng | 2017-02-14 |
| 9564420 | Functional block stacked 3DIC and method of making same | Kuo-Chung Yee, Chih-Hang Tung | 2017-02-07 |