Issued Patents All Time
Showing 101–125 of 137 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9287440 | Method of manufacturing a semiconductor device including through silicon plugs | Chen-Hua Yu, Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Chien Ling Hwang | 2016-03-15 |
| 9263511 | Package with metal-insulator-metal capacitor and method of manufacturing the same | Chen-Hua Yu, Shang-Yun Hou, Wen-Chih Chiou, Der-Chyang Yeh, Chiung-Han Yeh | 2016-02-16 |
| 9230902 | Interconnect structure for wafer level package | Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Shin-Puu Jeng | 2016-01-05 |
| 9159678 | Semiconductor device and manufacturing method thereof | Li-Hui Cheng, Po-Hao Tsai | 2015-10-13 |
| 9142432 | Integrated fan-out package structures with recesses in molding compound | Po-Hao Tsai, Li-Hui Cheng, Jing-Cheng Lin | 2015-09-22 |
| 9117682 | Methods of packaging semiconductor devices and structures thereof | Jing-Cheng Lin, Yi-Hang Lin, Tsan-Hua Tung | 2015-08-25 |
| 9111914 | Fan out package, semiconductor device and manufacturing method thereof | Jing-Cheng Lin, Po-Hao Tsai | 2015-08-18 |
| 9093447 | Chip on wafer bonder | Chen-Hua Yu, Weng-Jin Wu, Jean Wang, Wen-Chih Chiou | 2015-07-28 |
| 9064879 | Packaging methods and structures using a die attach film | Jing-Cheng Lin, Nai-Wei Liu, Chin-Chuan Chang, Chen-Hua Yu, Shin-Puu Jeng +3 more | 2015-06-23 |
| 9048222 | Method of fabricating interconnect structure for package-on-package devices | Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh +1 more | 2015-06-02 |
| 9000584 | Packaged semiconductor device with a molding compound and a method of forming the same | Jing-Cheng Lin, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung | 2015-04-07 |
| 8994171 | Method and apparatus for a conductive pillar structure | Jung-Hua Chang, Cheng-Lin Huang, Nai-Wei Liu, Jing-Cheng Lin | 2015-03-31 |
| 8962392 | Underfill curing method using carrier | Chin-Fu Kao, Jing-Cheng Lin, Szu-Wei Lu | 2015-02-24 |
| 8952544 | Semiconductor device and manufacturing method thereof | Jing-Cheng Lin, Po-Hao Tsai | 2015-02-10 |
| 8946742 | Semiconductor package with through silicon vias | Chen-Hua Yu, Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Chien Ling Hwang | 2015-02-03 |
| 8941244 | Semiconductor device and manufacturing method thereof | Po-Hao Tsai, Jing-Cheng Lin, Long Hua Lee | 2015-01-27 |
| 8936966 | Packaging methods for semiconductor devices | Jing-Cheng Lin | 2015-01-20 |
| 8927412 | Multi-chip package and method of formation | Jing-Cheng Lin, Chen-Hua Yu, Der-Chyang Yeh | 2015-01-06 |
| 8928117 | Multi-chip package structure and method of forming same | Chen-Hua Yu, Jing-Cheng Lin, Der-Chyang Yeh | 2015-01-06 |
| 8916956 | Multiple die packaging interposer structure and method | Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Chien-Hsun Lee, Kai-Chiang Wu | 2014-12-23 |
| 8916972 | Adhesion between post-passivation interconnect structure and polymer | Jing-Cheng Lin, Min-Chen Lin, Yi-Hang Lin | 2014-12-23 |
| 8877554 | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices | Po-Hao Tsai, Jing-Cheng Lin | 2014-11-04 |
| 8872326 | Three dimensional (3D) fan-out packaging mechanisms | Jing-Cheng Lin, Chin-Chuan Chang | 2014-10-28 |
| 8829676 | Interconnect structure for wafer level package | Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Shin-Puu Jeng | 2014-09-09 |
| 8827695 | Wafer's ambiance control | Yi-Li Hsiao, Chen-Hua Yu, Jean Wang, Ming-Che Ho, Chien Ling Hwang | 2014-09-09 |