Issued Patents All Time
Showing 76–100 of 137 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9679783 | Molding wafer chamber | Jing-Cheng Lin, Chin-Chuan Chang, Szu-Wei Lu, Shin-Puu Jeng, Chen-Hua Yu | 2017-06-13 |
| 9673181 | Package on package (PoP) bonding structures | Jing-Cheng Lin, Po-Hao Tsai | 2017-06-06 |
| 9673098 | Methods of packaging semiconductor devices and structures thereof | Jing-Cheng Lin, Yi-Hang Lin, Tsan-Hua Tung | 2017-06-06 |
| 9662812 | Methods for molding integrated circuits | Chih-Hao Chen, Hsien-Wen Liu, Yi-Lin Tsai, Jing-Cheng Lin | 2017-05-30 |
| 9633895 | Integrated fan-out structure with guiding trenches in buffer layer | Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jing-Cheng Lin | 2017-04-25 |
| 9595510 | Structure and formation method for chip package | Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng | 2017-03-14 |
| 9583424 | Integrated circuit structure and method for reducing polymer layer delamination | Jing-Cheng Lin, Hsien-Wen Liu, Min-Chen Lin | 2017-02-28 |
| 9576910 | Semiconductor packaging structure and manufacturing method thereof | Chen-Hua Yu, Ming-Da Cheng | 2017-02-21 |
| 9570401 | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices | Po-Hao Tsai, Jing-Cheng Lin | 2017-02-14 |
| 9553000 | Interconnect structure for wafer level package | Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Shin-Puu Jeng | 2017-01-24 |
| 9466581 | Semiconductor package device and manufacturing method thereof | Nai-Wei Liu, Jing-Cheng Lin | 2016-10-11 |
| 9460987 | Interconnect structure for package-on-package devices and a method of fabricating | Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh +1 more | 2016-10-04 |
| 9431367 | Method of forming a semiconductor package | Jing-Cheng Lin, Chin-Chuan Chang | 2016-08-30 |
| 9425121 | Integrated fan-out structure with guiding trenches in buffer layer | Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jing-Cheng Lin | 2016-08-23 |
| 9406581 | Methods of packaging semiconductor devices and structures thereof | Jing-Cheng Lin, Yi-Hang Lin, Tsan-Hua Tung | 2016-08-02 |
| 9406598 | Package with a fan-out structure and method of forming the same | Yi-Chao Mao, Chin-Chuan Chang, Jing-Cheng Lin | 2016-08-02 |
| 9379080 | Method and apparatus for a conductive pillar structure | Jung-Hua Chang, Cheng-Lin Huang, Nai-Wei Liu, Jing-Cheng Lin | 2016-06-28 |
| 9378982 | Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package | Jing-Cheng Lin, Li-Hui Cheng | 2016-06-28 |
| 9373527 | Chip on package structure and method | Chen-Hua Yu, Der-Chyang Yeh, Kuo-Chung Yee | 2016-06-21 |
| 9368438 | Package on package (PoP) bonding structures | Jing-Cheng Lin, Po-Hao Tsai | 2016-06-14 |
| 9355973 | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices | Po-Hao Tsai, Jing-Cheng Lin | 2016-05-31 |
| 9337063 | Package for three dimensional integrated circuit | Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh +2 more | 2016-05-10 |
| 9312148 | Method of packaging a semiconductor device | Jing-Cheng Lin, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung | 2016-04-12 |
| 9312149 | Method for forming chip-on-wafer assembly | Jing-Cheng Lin, Cheng-Lin Huang, Szu-Wei Lu, Shin-Puu Jeng, Chen-Hua Yu | 2016-04-12 |
| 9299682 | Packaging methods for semiconductor devices | Jing-Cheng Lin | 2016-03-29 |